Lillian Pentecost

Orcid: 0000-0002-6204-1938

According to our database1, Lillian Pentecost authored at least 20 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Is the Future Cold or Tall? Design Space Exploration of Cryogenic and 3D Embedded Cache Memory.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

CompressionGPT: Evaluating Fault Tolerance of a Compressed Large Language Model.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

NVMSurvey: Recent Advances and Comparative Analysis of Emerging Non-Volatile Memories (eNVMs).
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022
NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Introducing Programming Concepts via A Social History of Computing.
Proceedings of the SIGCSE '21: The 52nd ACM Technical Symposium on Computer Science Education, 2021

EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

2020
EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP.
CoRR, 2020


2019
MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge.
IEEE Micro, 2019

MLPerf Training Benchmark.
CoRR, 2019

A 16nm 25mm<sup>2</sup> SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

CHAMPVis: Comparative Hierarchical Analysis of Microarchitectural Performance.
Proceedings of the IEEE/ACM International Workshop on Programming and Performance Visualization Tools, 2019

MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Application of Approximate Matrix Multiplication to Neural Networks and Distributed SLAM.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

MASR: A Modular Accelerator for Sparse RNNs.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
A Creative First Assignment in the Modern Graphics Pipeline.
Proceedings of the 39th Annual Conference of the European Association for Computer Graphics, 2018

Ares: a framework for quantifying the resilience of deep neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

On-chip deep neural network storage with multi-level eNVM.
Proceedings of the 55th Annual Design Automation Conference, 2018

2015
Accelerating dynamically typed languages with a virtual function cache.
Proceedings of the 2nd International Workshop on Hardware-Software Co-Design for High Performance Computing, 2015


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