Lieven Eeckhout

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01727-8, 2010

A Counter Architecture for Online DVFS Profitability Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Fast, Accurate, and Validated Full-System Software Simulation of x86 Hardware.

[BibT_eX]

[DOI]

Frederick Ryckbosch

Stijn Polfliet

IEEE Micro, 2010

Per-Thread Cycle Accounting.

[BibT_eX]

[DOI]

IEEE Micro, 2010

Workload Reduction and Generation Techniques.

[BibT_eX]

[DOI]

IEEE Micro, 2010

Scenario-Based Resource Prediction for QoS-Aware Media Processing.

[BibT_eX]

[DOI]

Computer, 2010

Evaluating iterative optimization across 1000 datasets.

[BibT_eX]

[DOI]

Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors.

[BibT_eX]

[DOI]

Arun A. Nair

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Modeling critical sections in Amdahl's law and its implications for multicore design.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Benchmark synthesis for architecture and compiler exploration.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Interval simulation: Raising the level of abstraction in architectural simulation.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Automated just-in-time compiler tuning.

[BibT_eX]

[DOI]

Proceedings of the CGO 2010, 2010

Probabilistic job symbiosis modeling for SMT processor scheduling.

[BibT_eX]

[DOI]

Stefan Valentin Gheorghita

Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009

System-scenario-based design of dynamic embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

A mechanistic performance model for superscalar out-of-order processors.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2009

Branch Predictor Warmup for Sampled Simulation through Branch History Matching.

[BibT_eX]

[DOI]

Simon Kluyskens

Trans. High Perform. Embed. Archit. Compil., 2009

Chip Multiprocessor Design Space Exploration through Statistical Simulation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

Memory-level parallelism aware fetch policies for simultaneous multithreading processors.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

A Methodology for Analyzing Commercial Processor Performance Numbers.

[BibT_eX]

[DOI]

Computer, 2009

Finding Stress Patterns in Microprocessor Workloads.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2009

MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.

[BibT_eX]

[DOI]

Kenzo Van Craeynest

Proceedings of the High Performance Embedded Architectures and Compilers, 2009

Per-thread cycle accounting in SMT processors.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2008

Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

Distilling the essence of proprietary workloads into miniature benchmarks.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2008

System-Level Performance Metrics for Multiprogram Workloads.

[BibT_eX]

[DOI]

IEEE Micro, 2008

Accurate and Efficient Cache Warmup for Sampled Processor Simulation Through NSL-BLRL.

[BibT_eX]

[DOI]

Filip Hellebaut

Comput. J., 2008

Sampled Processor Simulation- A Survey.

[BibT_eX]

Adv. Comput., 2008

Java performance evaluation through rigorous replay compilation.

[BibT_eX]

[DOI]

Dries Buytaert

Proceedings of the 23rd Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2008

Characterizing the Unique and Diverse Behaviors in Existing and Emerging General-Purpose and Domain-Specific Benchmark Suites.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Automated microprocessor stressmark generation.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.

[BibT_eX]

[DOI]

James E. Smith

Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Automated hardware-independent scenario identification.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Cole: compiler optimization level exploration.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Code Generation and Optimization (CGO 2008), 2008

Dispersing proprietary applications as benchmarks through code mutation.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007

GCH: Hints for Triggering Garbage Collections.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2007

Java object header elimination for reduced memory consumption in 64-bit virtual machines.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2007

Microarchitecture-Independent Workload Characterization.

[BibT_eX]

[DOI]

IEEE Micro, 2007

A Top-Down Approach to Architecting CPI Component Performance Counters.

[BibT_eX]

[DOI]

IEEE Micro, 2007

Exploiting program phase behavior for energy reduction on multi-configuration processors.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Analyzing commercial processor performance numbers for predicting performance of applications of interest.

[BibT_eX]

[DOI]

Hendrik Blockeel

Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007

Adding rigorous statistics to the Java benchmarker's toolbox.

[BibT_eX]

[DOI]

Dries Buytaert

Proceedings of the Companion to the 22nd Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2007

Statistically rigorous java performance evaluation.

[BibT_eX]

[DOI]

Dries Buytaert

Proceedings of the 22nd Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2007

Using hpm-sampling to drive dynamic compilation.

[BibT_eX]

[DOI]

Proceedings of the 22nd Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2007

Exploiting Video Stream Similarity for Energy-Efficient Decoding.

[BibT_eX]

[DOI]

Proceedings of the Advances in Multimedia Modeling, 2007

Representative Multiprogram Workloads for Multithreaded Processor Simulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Symposium on Workload Characterization, 2007

Statistical simulation of chip multiprocessors running multi-program workloads.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

A Memory-Level Parallelism Aware Fetch Policy for SMT Processors.

[BibT_eX]

[DOI]

Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

Branch History Matching: Branch Predictor Warmup for Sampled Simulation.

[BibT_eX]

[DOI]

Simon Kluyskens

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Object-Relative Addressing: Compressed Pointers in 64-Bit Java Virtual Machines.

[BibT_eX]

[DOI]

Proceedings of the ECOOP 2007 - Object-Oriented Programming, 21st European Conference, Berlin, Germany, July 30, 2007

Resource prediction for media stream decoding.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Exploring the Application Behavior Space Using Parameterized Synthetic Benchmarks.

[BibT_eX]

[DOI]

Ajay M. Joshi

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

Studying Compiler-Microarchitecture Interactions through Interval Analysis.

[BibT_eX]

[DOI]

James E. Smith

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Measuring Benchmark Similarity Using Inherent Program Characteristics.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

64-bit versus 32-bit Virtual Machines for Java.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2006

Efficient Sampling Startup for SimPoint.

[BibT_eX]

[DOI]

IEEE Micro, 2006

Yet shorter warmup by combining no-state-loss and MRRL for sampled LRU cache simulation.

[BibT_eX]

[DOI]

J. Syst. Softw., 2006

Pattern-driven prefetching for multimedia applications on embedded processors.

[BibT_eX]

[DOI]

Hassan Sbeyti

J. Syst. Archit., 2006

Improved composite confidence mechanisms for a perceptron branch predictor.

[BibT_eX]

[DOI]

Veerle Desmet

J. Syst. Archit., 2006

The Future of Simulation: A Field of Dreams.

[BibT_eX]

[DOI]

Computer, 2006

Javana: a system for building customized Java program analysis tools.

[BibT_eX]

[DOI]

Proceedings of the 21th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2006

Building Java program analysis tools using Javana.

[BibT_eX]

[DOI]

Proceedings of the Companion to the 21th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2006

Evaluating the efficacy of statistical simulation for design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Characterizing the branch misprediction penalty.

[BibT_eX]

[DOI]

James E. Smith

Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Considering all starting points for simultaneous multithreading simulation.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Evaluating Benchmark Subsetting Approaches.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

Comparing Benchmarks Using Key Microarchitecture-Independent Characteristics.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual International Conference on Supercomputing, 2006

Accurate memory data flow modeling in statistical simulation.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual International Conference on Supercomputing, 2006

Efficient design space exploration of high performance embedded out-of-order processors.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Space-Efficient 64-bit Java Objects through Selective Typed Virtual Addressing.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

A performance counter architecture for computing accurate CPI components.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

NSL-BLRL: Efficient CacheWarmup for Sampled Processor Simulation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2006

Performance prediction based on inherent program similarity.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

Optimal sample length for efficient cache simulation.

[BibT_eX]

[DOI]

J. Syst. Archit., 2005

SMA: A Self-Monitored Adaptive Cache Warm-Up Scheme for Microprocessor Simulation.

[BibT_eX]

[DOI]

Yue Luo

Int. J. Parallel Program., 2005

Middleware benchmarking: approaches, results, experiences.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2005

BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation.

[BibT_eX]

[DOI]

Comput. J., 2005

Offline Phase Analysis and Optimization for Multi-configuration Processors.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

Garbage Collection Hints.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2005

Efficient Sampling Startup for Sampled Processor Simulation.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2005

A Detailed Study on Phase Predictors.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

Comparing Low-Level Behavior of SPEC CPU and Java Workloads.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction.

[BibT_eX]

[DOI]

Veerle Desmet

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004

Speeding Up Architectural Simulations for High-Performance Processors.

[BibT_eX]

[DOI]

Simul., 2004

Efficient simulation of trace samples on parallel machines.

[BibT_eX]

[DOI]

Parallel Comput., 2004

How accurate should early design stage power/performance tools be? A case study with statistical simulation.

[BibT_eX]

[DOI]

J. Syst. Softw., 2004

Efficient architectural design of high performance microprocessors.

[BibT_eX]

[DOI]

Adv. Comput., 2004

Low-level behavioral analysis of the JVT/AVC decoder.

[BibT_eX]

[DOI]

Proceedings of the Visual Communications and Image Processing 2004, 2004

Self-Monitored Adaptive Cache Warm-Up for Microprocessor Simulation.

[BibT_eX]

[DOI]

Yue Luo

Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Method-level phase behavior in java workloads.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2004

Bottleneck analysis in java applications using hardware performance monitors.

[BibT_eX]

[DOI]

Proceedings of the Companion to the 19th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2004

Efficient architectural design of high performance microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies.

[BibT_eX]

[DOI]

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Adaptive Prefetching for Multimedia Applications in Embedded Systems.

[BibT_eX]

[DOI]

Hassan Sbeyti

Proceedings of the 2004 Design, 2004

2003

Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox.

[BibT_eX]

[DOI]

IEEE Micro, 2003

Quantifying behavioral differences between multimedia and general-purpose workloads.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

Quantifying the Impact of Input Data Sets on Program Behavior and its Applications.

[BibT_eX]

[DOI]

Hans Vandierendonck

J. Instr. Level Parallelism, 2003

Designing Computer Architecture Research Workloads.

[BibT_eX]

[DOI]

Hans Vandierendonck

Computer, 2003

Comparing Multiported Cache Schemes.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

How java programs interact with virtual machines at the microarchitectural level.

[BibT_eX]

[DOI]

Proceedings of the 2003 ACM SIGPLAN Conference on Object-Oriented Programming Systems, 2003

Efficient Microprocessor Design Space Exploration through Statistical Simulatio.

[BibT_eX]

[DOI]

Dirk Stroobandt

Proceedings of the Proceedings 36th Annual Simulation Symposium (ANSS-36 2003), Orlando, Florida, USA, March 30, 2003

2002

Workload Design: Selecting Representative Program-Input Pairs.

[BibT_eX]

[DOI]

Hans Vandierendonck

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001

Early design phase power/performance modeling through statistical simulation.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001

Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000

Early design stage exploration of fixed-length block structured architectures.

[BibT_eX]

[DOI]

J. Syst. Archit., 2000

Performance analysis through synthetic trace generation.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

On the Feasibility of Fixed-Length Block Structured Architectures.

[BibT_eX]

[DOI]

Proceedings of the 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January, 2000

1999

Estimating IPC of a block structured instruction set architecture in an early design stage.

[BibT_eX]

Proceedings of the Parallel Computing: Fundamentals & Applications, 1999

Investigating the Implementation of a Block Structured Architecture in an Early Design Stage.

[BibT_eX]

[DOI]