Lien-Fei Chen
According to our database1,
Lien-Fei Chen
authored at least 18 papers
between 2003 and 2016.
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Bibliography
2016
IEEE J. Solid State Circuits, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2010
Hybrid parallel motion estimation architecture based on fast top-winners search algorithm.
IEEE Trans. Consumer Electron., 2010
A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC.
IEEE Trans. Consumer Electron., 2010
2009
A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform.
IEEE Trans. Consumer Electron., 2009
Hardware Efficient Coarse-to-fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the IEEE International Conference on Acoustics, 2009
2008
A high-speed 2-D transform architecture with unique kernel for multi-standard video applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
2006
A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications.
IEICE Trans. Electron., 2006
Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
2005
A two-way SIMD-based reconfigurable computing architecture for multimedia applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
A novel memoryless AES cipher architecture for networking applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A performance-driven configurable motion estimator for full-search block-matching algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
VLSI architecture of the reconfigurable computing engine for digital signal processing applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A high data-reuse architecture with double-slice processing for full-search block-matching algorithm.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003