Lide Duan
Orcid: 0000-0001-5819-5283
According to our database1,
Lide Duan
authored at least 29 papers
between 2007 and 2022.
Collaborative distances:
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Bibliography
2022
184QPS/W 64Mb/mm<sup>2</sup>3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
IEEE Trans. Parallel Distributed Syst., 2020
Frontiers Comput. Sci., 2020
2019
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019
Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019
2018
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 2018 Annual IEEE International Systems Conference, 2018
Efficient Allocation and Heterogeneous Composition of NVM Crossbar Arrays for Deep Learning Acceleration.
Proceedings of the 37th IEEE International Performance Computing and Communications Conference, 2018
CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration.
Proceedings of the 32nd International Conference on Supercomputing, 2018
2017
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance.
ACM Trans. Embed. Comput. Syst., 2017
RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017
Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017
2016
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors.
Microprocess. Microsystems, 2015
Optimizing Cloud Data Center Energy Efficiency via Dynamic Prediction of CPU Idle Intervals.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015
2014
Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules.
IEEE Trans. Computers, 2014
Design configuration selection for hard-error reliable processors via statistical rules.
Microprocess. Microsystems, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing.
IEEE Trans. Dependable Secur. Comput., 2013
2012
Optimal microarchitectural design configuration selection for processor hard-error reliability.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
Universal rules guided design parameter selection for soft error resilient processors.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011
2010
Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions.
IEEE Trans. Computers, 2010
Comput. Commun., 2010
2009
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
2007
Proceedings of the Global Communications Conference, 2007