Liang-Chia Cheng

According to our database¹, Liang-Chia Cheng authored at least 17 papers between 2008 and 2017.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2017

Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Thermal modeling and design on smartphones with heat pipe cooling technique.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.

[BibT_eX]

[DOI]

Integr., 2016

2015

Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Incremental transient simulation of power grid.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2014

Variation aware optimal threshold voltage computation for on-chip noise sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Benchmarking for research in power delivery networks of three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2008

Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Liang-Chia Cheng

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...