Li-Ming Denq

According to our database1, Li-Ming Denq authored at least 13 papers between 2003 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
3D-IC BISR for stacked memories using cross-die spares.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
A Memory Built-In Self-Repair Scheme Based on Configurable Spares.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
Proceedings of the 48th Design Automation Conference, 2011

2010
SOC Test Architecture and Method for 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Economic Analysis of the HOY Wireless Test Methodology.
IEEE Des. Test Comput., 2010

2009
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories.
IEEE Des. Test Comput., 2009

2008
Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A prototype of a wireless-based test system.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories.
Proceedings of the 16th Asian Test Symposium, 2007

2006
An Enhanced SRAM BISR Design with Reduced Timing Penalty.
Proceedings of the 15th Asian Test Symposium, 2006

2004
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

An SOC Test Integration Platform and Its Industrial Realization.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003


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