Li Jiang
Orcid: 0000-0002-7353-8798Affiliations:
- Shanghai Jiao Tong University, Department of Computer Science and Engineering, China
- Chinese University of Hong Kong, Department of Computer Science and Engineering, Hong Kong (PhD 2013)
According to our database1,
Li Jiang
authored at least 112 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
-
on dl.acm.org
On csauthors.net:
Bibliography
2024
ERA-BS: Boosting the Efficiency of ReRAM-Based PIM Accelerator With Fine-Grained Bit-Level Sparsity.
IEEE Trans. Computers, September, 2024
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
SPARK: Scalable and Precision-Aware Acceleration of Neural Networks via Efficient Encoding.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
PSQ: An Automatic Search Framework for Data-Free Quantization on PIM-based Architecture.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
HyperNode: An Efficient Node Classification Framework Using HyperDimensional Computing.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Computers, 2022
CoRR, 2022
L3E-HD: A Framework Enabling Efficient Ensemble in High-Dimensional Space for Language Tasks.
Proceedings of the SIGIR '22: The 45th International ACM SIGIR Conference on Research and Development in Information Retrieval, Madrid, Spain, July 11, 2022
Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Randomize and Match: Exploiting Irregular Sparsity for Energy Efficient Processing in SNNs.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
SpikeConverter: An Efficient Conversion Framework Zipping the Gap between Artificial Neural Networks and Spiking Neural Networks.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022
2021
DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays.
IEEE Trans. Very Large Scale Integr. Syst., 2021
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization.
ACM Trans. Reconfigurable Technol. Syst., 2021
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.
CoRR, 2021
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021
ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Improving Neural Network Efficiency via Post-training Quantization with Adaptive Floating-Point.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021
SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Lazy-WL: A Wear-aware Load Balanced Data Redistribution Method for Efficient SSD Array Scaling.
Proceedings of the IEEE International Conference on Cluster Computing, 2021
Proceedings of the CIKM '21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1, 2021
Proceedings of the 14th International Congress on Image and Signal Processing, 2021
2020
Measurement Scheduling for Cooperative Localization in Resource-Constrained Conditions.
IEEE Robotics Autom. Lett., 2020
AUSN: Approximately Uniform Quantization by Adaptively Superimposing Non-uniform Distribution for Deep Neural Networks.
CoRR, 2020
LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method.
ACM Trans. Design Autom. Electr. Syst., 2019
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Parallel Distributed Syst., 2018
Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit.
ACM Trans. Design Autom. Electr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Concurr. Comput. Pract. Exp., 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 15th International Symposium on Parallel and Distributed Computing, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist.
Proceedings of the 2015 IEEE International Test Conference, 2015
On diagnosable and tunable 3D clock network design for lifetime reliability enhancement.
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
AgentDiag: An agent-assisted diagnostic framework for board-level functional failures.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009