Li Jiang

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

HyperNode: An Efficient Node Classification Framework Using HyperDimensional Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for SNN Acceleration.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

HyperAttack: An Efficient Attack Framework for HyperDimensional Computing.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN.

[BibT_eX]

[DOI]

CoRR, 2022

DNN Training Acceleration via Exploring GPGPU Friendly Sparsity.

[BibT_eX]

[DOI]

CoRR, 2022

CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction.

[BibT_eX]

[DOI]

CoRR, 2022

L3E-HD: A Framework Enabling Efficient Ensemble in High-Dimensional Space for Language Tasks.

[BibT_eX]

[DOI]

Proceedings of the SIGIR '22: The 45th International ACM SIGIR Conference on Research and Development in Information Retrieval, Madrid, Spain, July 11, 2022

Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Randomize and Match: Exploiting Irregular Sparsity for Energy Efficient Processing in SNNs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores.

[BibT_eX]

[DOI]

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

SpikeConverter: An Efficient Conversion Framework Zipping the Gap between Artificial Neural Networks and Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021

DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Yongpan Liu

Huazhong Yang

Xueqing Li

IEEE Trans. Very Large Scale Integr. Syst., 2021

BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2021

ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Skimming and Scanning for Untrimmed Video Action Recognition.

[BibT_eX]

[DOI]

CoRR, 2021

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.

[BibT_eX]

[DOI]

CoRR, 2021

On Workload-Aware DRAM Failure Prediction in Large-Scale Data Centers.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

PIPArch: Programmable Image Processing Architecture Using Sliding Array.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Ternary Memristive Logic-in-Memory Design for Fast Data Scan.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Improving Neural Network Efficiency via Post-training Quantization with Adaptive Floating-Point.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Lazy-WL: A Wear-aware Load Balanced Data Redistribution Method for Efficient SSD Array Scaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Cluster Computing, 2021

AdaptiveGCN: Efficient GCN Through Adaptively Sparsifying Graphs.

[BibT_eX]

[DOI]

Proceedings of the CIKM '21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1, 2021

Skimming and Scanning for Efficient Action Recognition in Untrimmed Videos.

[BibT_eX]

[DOI]

Proceedings of the 14th International Congress on Image and Signal Processing, 2021

2020

Measurement Scheduling for Cooperative Localization in Resource-Constrained Conditions.

[BibT_eX]

[DOI]

Qi Yan

Solmaz S. Kia

IEEE Robotics Autom. Lett., 2020

AUSN: Approximately Uniform Quantization by Adaptively Superimposing Non-uniform Distribution for Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2020

LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection.

[BibT_eX]

[DOI]

Xingyi Wang

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Approximate Random Dropout for DNN training acceleration in GPGPU.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

System-level hardware failure prediction using deep learning.

[BibT_eX]

[DOI]

Xiaoyi Sun

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A sharing-aware L1.5D cache for data reuse in GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

CNFET-Based High Throughput SIMD Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Approximate Random Dropout.

[BibT_eX]

[DOI]

CoRR, 2018

Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

AXNet: approximate computing using an end-to-end trainable neural network.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

In-growth test for monolithic 3D integrated SRAM.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ReCom: An efficient resistive accelerator for compressed deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Incorporating selective victim cache into GPGPU for high-performance computing.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2017

Fault clustering technique for 3D memory BISR.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

On Quality Trade-off Control for Approximate Computing Using Iterative Training.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs.

[BibT_eX]

[DOI]

Naifeng Jing

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Defect tolerance for CNFET-based SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Applying Victim Cache in High Performance GPGPU Computing.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on Parallel and Distributed Computing, 2016

CNFET-based high throughput register file architecture.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

A Low-Cost TSV Test and Diagnosis Scheme Based on Binary Search Method.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Timing-driven placement for carbon nanotube circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

On microarchitectural modeling for CNFET-based circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Fault-Tolerant 3D-NoC Architecture and Design: Recent Advances and Challenges.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

On diagnosable and tunable 3D clock network design for lifetime reliability enhancement.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Bank stealing for conflict mitigation in GPGPU Register File.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Building Fuel Powered Supercomputing Data Center at Low Cost.

[BibT_eX]

[DOI]

Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

A novel TSV probing technique with adhesive test interposer.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Jump test for metallic CNTs in CNFET-based SRAM.

[BibT_eX]

[DOI]

Feng Xie

Xiaoyao Liang

Naifeng Jing

Proceedings of the 52nd Annual Design Automation Conference, 2015

On test syndrome merging for reasoning-based board-level functional fault diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013

On Effective Through-Silicon Via Repair for 3-D-Stacked ICs.

[BibT_eX]

[DOI]

Bill Eklow

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

AgentDiag: An agent-assisted diagnostic framework for board-level functional failures.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

On effective and efficient in-field TSV repair for stacked 3D ICs.

[BibT_eX]

[DOI]

Fangming Ye

Bill Eklow

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.

[BibT_eX]

[DOI]

T. M. Mak

IEEE Trans. Very Large Scale Integr. Syst., 2012

On effective TSV repair for 3D-stacked ICs.

[BibT_eX]

[DOI]

Bill Eklow

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Yield enhancement for 3D-stacked ICs: Recent advances and challenges.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2010

Modeling TSV open defects in 3D-stacked DRAM.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Yield enhancement for 3D-stacked memory by redundancy sharing across dies.

[BibT_eX]

[DOI]

Rong Ye

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint.

[BibT_eX]

[DOI]

T. M. Mak

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Test architecture design and optimization for three-dimensional SoCs.

[BibT_eX]

[DOI]

Lin Huang