Li-C. Wang
Orcid: 0000-0003-4851-8004Affiliations:
- University of California, Santa Barbara, CA, USA
According to our database1,
Li-C. Wang
authored at least 186 papers
between 1991 and 2024.
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Bibliography
2024
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
2023
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE International Test Conference, 2023
2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Test Conference in Asia, 2022
2021
Proceedings of the IEEE International Test Conference, 2021
2020
Proceedings of the IEEE International Test Conference, 2020
2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the IEEE International Test Conference in Asia, 2019
Facilitating Deployment Of A Wafer-Based Analytic Software Using Tensor Methods: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the 2018 International Symposium on Physical Design, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Des. Test, 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the IEEE International Test Conference, 2017
Systematic defect detection methodology for volume diagnosis: A data mining perspective.
Proceedings of the IEEE International Test Conference, 2017
Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery.
Proceedings of the 54th Annual Design Automation Conference, 2017
Feature extraction from design documents to enable rule learning for improving assertion coverage.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs.
J. Electron. Test., 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the International Symposium on Physical Design, 2013
Simulation knowledge extraction and reuse in constrained random processor verification.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Functional test content optimization for peak-power validation - An experimental study.
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the 2011 IEEE International Test Conference, 2011
Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Des. Test Comput., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Correlating system test Fmax with structural test Fmax and process monitoring measurements.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained.
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
IEEE Des. Test Comput., 2007
Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.
IEEE Des. Test Comput., 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Enhancing signal controllability in functional test-benches through automatic constraint extraction.
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
An incremental learning framework for estimating signal controllability in unit-level verification.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
IEEE Trans. Computers, 2006
Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective.
Proceedings of the 2006 IEEE International Test Conference, 2006
An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space.
Proceedings of the 2006 IEEE International Test Conference, 2006
Simulation-based functional test justification using a decision-digram-based Boolean data miner.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Hardware and Software, 2006
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
ACM Trans. Design Autom. Electr. Syst., 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 2005 Design, 2005
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Critical path selection for delay fault testing based upon a statistical timing model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Des. Test Comput., 2004
IEEE Des. Test Comput., 2004
IEEE Des. Test Comput., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEEE Des. Test Comput., 2003
Des. Autom. Embed. Syst., 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
Proceedings of the 40th Design Automation Conference, 2003
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Experience in critical path selection for deep sub-micron delay test and timing validation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Validation and Verification of Complex Digital Systems: A Practical Perspective.
Proceedings of the 3rd Latin American Test Workshop, 2002
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
On theoretical and practical considerations of path selection for delay fault testing.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 39th Design Automation Conference, 2002
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation.
Proceedings of the 39th Design Automation Conference, 2002
2001
IEEE Des. Test Comput., 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Verification and Validation of Complex Digital Systems: An Industrial Perspective.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of ASP-DAC 2001, 2001
2000
On Efficiently Producing Quality Tests for Custom Circuits in PowerPC<sup>TM</sup> Microprocessors.
J. Electron. Test., 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
J. Electron. Test., 1999
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.
ACM Trans. Design Autom. Electr. Syst., 1998
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.
J. Electron. Test., 1998
On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.
Proceedings of the 1998 Design, 1998
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation.
Proceedings of the 35th Conference on Design Automation, 1998
1997
A New Validation Methodology Combining Test and Formal Verification for PowerPC<sup>TM</sup> Microprocessor Arrays.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1993
Proceedings of the 5th Annual ACM Symposium on Parallel Algorithms and Architectures, 1993
1991
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991