Levent Aksoy

Samuel Pagliarini

CoRR, 2024

CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks.

[BibT_eX]

[DOI]

Muhammad Yasin

Samuel Pagliarini

Proceedings of the 25th IEEE Latin American Test Symposium, 2024

KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking.

[BibT_eX]

[DOI]

Muhammad Yasin

Samuel Pagliarini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Multiplierless Design of High-Speed Very Large Constant Multiplications.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Hybrid Protection of Digital FIR Filters.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., June, 2023

Resynthesis-based Attacks Against Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022

Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Multiplierless Design of Very Large Constant Multiplications in Cryptography.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Hardware Obfuscation of Digital FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021

Realization of Logic Functions Using Switching Lattices Under a Delay Constraint.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

High-level Intellectual Property Obfuscation via Decoy Constants.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Side-Channel Attacks on Triple Modular Redundancy Schemes.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices.

[BibT_eX]

[DOI]

Mohammadreza Esmali Nojehdeh

IEEE Trans. Computers, 2020

Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks.

[BibT_eX]

[DOI]

Mohammadreza Esmali Nojehdeh

Sajjad Parvin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Novel Method for the Realization of Complex Logic Functions using Switching Lattices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

CMOS Implementation of Switching Lattices.

[BibT_eX]

[DOI]

Ismail Cevik

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling.

[BibT_eX]

[DOI]

Serzat Safaltin

Oguz Gencer

Muhammed Ceylan Morgül

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2016

A novel method for the approximation of multiplierless constant matrix vector multiplication.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2016

2015

Exact and Approximate Algorithms for the Filter Design Optimization Problem.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2015

Approximation of multiple constant multiplications using minimum look-up tables on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Multiplierless Design of Folded DSP Blocks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

ECHO: A novel method for the multiplierless design of constant array vector multiplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Optimization of design complexity in time-multiplexed constant multiplications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Towards the least complex time-multiplexed constant multiplication.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

SIREN: a depth-first search algorithm for the filter design optimization problem.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Exploration of tradeoffs in the design of integer cosine transforms for image compression.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

Optimization Algorithms for the Multiplierless Realization of Linear Transforms.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications.

[BibT_eX]

[DOI]

Integr., 2012

Multiple tunable constant multiplications: Algorithms and applications.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Design of low-complexity digital finite impulse response filters on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Finding the optimal tradeoff between area and delay in multiple constant multiplications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

Multiplierless Design of Linear DSP Transforms.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011

A hybrid algorithm for the optimization of area and delay in linear DSP transforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Optimization of area in digit-serial Multiple Constant Multiplications at gate-level.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Efficient shift-adds design of digit-serial multiple constant multiplications.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Design of low-power multiple constant multiplications using low-complexity minimum depth operations.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Optimization of gate-level area in high throughput Multiple Constant Multiplications.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Search algorithms for the multiple constant multiplications problem: Exact and approximate.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2010

Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability

[BibT_eX]

[DOI]

CoRR, 2010

Design of low-complexity and high-speed digital Finite Impulse Response filters.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Design of low complexity digital FIR filters.

[BibT_eX]

[DOI]

Diego Jaccottet

Eduardo Costa

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2008

Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Area optimization algorithms in high-speed digital FIR filter synthesis.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

An approximate algorithm for the multiple constant multiplications problem.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

2007

Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Minimum number of operations under a general number representation for digital filter synthesis.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Optimization of Area in Digital FIR Filters using Gate-Level Metrics.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

An Evolutionary Local Search Algorithm for the Satisfiability Problem.

[BibT_eX]

[DOI]