Leonard Lee

According to our database, Leonard Lee authored at least 6 papers between 2003 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space.

Leonard Lee, Li-C. Wang

Proceedings of the 2006 IEEE International Test Conference, 2006

On bounding the delay of a critical path.

Leonard Lee, Li-C. Wang

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

On Silicon-Based Speed Path Identification.

Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

On Generating Tests to Cover Diverse Worst-Case Timing Corners.

Leonard Lee, Sean H. Wu, Charles H.-P. Wen, Li-C. Wang

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

A path-based methodology for post-silicon timing validation.

Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.

Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003