Leon Stok

Orcid: 0000-0003-1219-4319

According to our database1, Leon Stok authored at least 40 papers between 1989 and 2023.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2004, "For the development and application of high-level and logic synthesis algorithms.".

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
Quantum Challenges for EDA.
Proceedings of the 2023 International Symposium on Physical Design, 2023

2021
Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology.
IEEE Des. Test, 2021

EDA and Quantum Computing: The key role of Quantum Circuits.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

2020
EDA and Quantum Computing: a symbiotic relationship?
IEEE Des. Test, 2020

2018
Concurrent High Performance Processor Design: From Logic to PD in Parallel.
Proceedings of the 2018 International Symposium on Physical Design, 2018

EDA3.0: Implications to Logic Synthesis.
Proceedings of the Advanced Logic Synthesis, 2018

2014
The Next 25 Years in EDA: A Cloudy Future?
IEEE Des. Test, 2014

2013
Developing Parallel EDA Tools [The Last Byte].
IEEE Des. Test, 2013

2010
EDA challenges and options: investing for the future.
Proceedings of the 47th Design Automation Conference, 2010

2009
From restrictive to prescriptive design.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Variability and New Design Paradigms.
IEEE Des. Test Comput., 2008

2007
DAC Highlights.
IEEE Des. Test Comput., 2007

2005
Minimizing power with flexible voltage islands.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Keeping hot chips cool.
Proceedings of the 42nd Design Automation Conference, 2005

2003
Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

There is life left in ASICs.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Pushing ASIC performance in a power envelope.
Proceedings of the 40th Design Automation Conference, 2003

2002
Layout Driven Decomposition with Congestion Consideration.
Proceedings of the 2002 Design, 2002

2001
Congestion Aware Layout Driven Logic Synthesis.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
Combinatorial cell design for CMOS libraries.
Integr., 2000

Regularity Driven Logic Synthesis.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Transformational Placement and Synthesis.
Proceedings of the 2000 Design, 2000

Timing closure: the solution and its problems.
Proceedings of ASP-DAC 2000, 2000

1999
Wavefront Technology Mapping.
Proceedings of the 1999 Design, 1999

1998
Don't cares in synthesis: theoretical pitfalls and practical solutions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Gate-size selection for standard cell libraries.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Timing analysis and optimization: from devices to systems (tutorial).
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Retiming revisited and reversed.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

BooleDozer: Logic synthesis for ASICs.
IBM J. Res. Dev., 1996

1995
High-level synthesis in an industrial environment.
IBM J. Res. Dev., 1995

Be careful with don't cares.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Efficient use of large don't cares in high-level and logic synthesis.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Improving initialization through reversed retiming.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Data path synthesis.
Integr., 1994

Is high-level synthesis marketable? (panel).
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

1992
Foreground memory management in data path synthesis.
Int. J. Circuit Theory Appl., 1992

False loops through resource sharing.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Flexible Block-Multiplier Generation.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Interconnect optimisation during data path allocation.
Proceedings of the European Design Automation Conference, 1990

1989
From Network to Artwork.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989


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