Leomar Soares
According to our database1,
Leomar Soares
authored at least 2 papers
in 2019.
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Bibliography
2019
Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019