Leo Filippini

Orcid: 0000-0003-1139-4052

According to our database1, Leo Filippini authored at least 14 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2024
Design Automation for Charge Recovery Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2021
Scalable Resonant Power Clock Generation for Adiabatic Logic Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020
Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
The Adiabatically Driven StrongARM Comparator.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Low Swing - Low Frequency Rotary Traveling Wave Oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A charge recovery logic system bus.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Charge recovery implementation of an analog comparator: Initial results.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Wireless charge recovery system for implanted electroencephalography applications in mice.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Stability of Rotary Traveling Wave Oscillators under process variations and NBTI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Charge recovery logic for thermal harvesting applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
FinFET-Based Low-Swing Clocking.
ACM J. Emerg. Technol. Comput. Syst., 2015

A wirelessly powered system with charge recovery logic.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014


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