Leneesh Raghavan

According to our database, Leneesh Raghavan authored at least 7 papers between 2009 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A Fast T&H Overcurrent Detector for a Spinning Hall Current Sensor With Ping-Pong and Chopping Techniques.

Yongjia Li, Mario Motz, Leneesh Raghavan

IEEE J. Solid State Circuits, 2019

2018

A Signal and Offset T&H Frontend for Spinning Hall Sensors with Ping-Pong and Chopping Techniques.

Yongjia Li, Mario Motz, Leneesh Raghavan

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2012

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.

Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.

Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

2010

Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link.

Leneesh Raghavan, Ting Wu

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009

A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link.

Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Reduction of Current Mismatch in PLL Charge Pump.

H. Md. Shuaeb Fazeel, Leneesh Raghavan, Chandrasekaran Srinivasaraman, Manish Jain

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009