Leilei Huang

Orcid: 0000-0002-8900-4109

According to our database1, Leilei Huang authored at least 33 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Benchmark Dataset and Pair-Wise Ranking Method for Quality Evaluation of Night-Time Image Enhancement.
IEEE Trans. Multim., 2024

A 10.31 ENOB 3.125MHz BW fully passive 2nd-order noise-shaping SAR ADC for low cost IoT sensor networks.
IEICE Electron. Express, 2024

23.1 A 44μW IoT Tag Enabling 1μs Synchronization Accuracy and OFDMA Concurrent Communication with Software-Defined Modulation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A PCA Acceleration Algorithm For WiFi Sensing And Its Hardware Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

An 8K@120fps Hardware Implementation for Decoder-Side Motion Vector Refinement in VVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A Real-Time Respiration Monitoring System Using WiFi Sensing Based on the Concentric Circle Model.
IEEE Trans. Biomed. Circuits Syst., April, 2023

A 88%-Peak-Efficiency 10-mV-Voltage-Ripple Dual-Mode Switched-Capacitor DC-DC Converter for Ultra-Low-Power Battery Management.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 3.84 GHz 32 fs RMS Jitter Over-Sampling PLL with High-Gain Cross-Switching Phase Detector.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A High-Gain and Low-Noise Mixer with Hybrid $G_{m}$-Boosting for 5G FR2 Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An Error-Surface-Based Fractional Motion Estimation Algorithm and Hardware Implementation for VVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Fast QTMT Partition for VVC Intra Coding Using U-Net Framework.
Proceedings of the IEEE International Conference on Image Processing, 2023

A Low-Power 8-to-12-bit Reconfigurable SAR ADC for Portable Ultrasound Systems.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

A Dynamic-Texture-Guided Fast Algorithm for Geometric Partitioning Mode of VVC.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A High-Throughput Luma Mapping with Chroma Scaling Decoder for Versatile Video Coding.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A Fast CABAC Hardware Design for Accelerating the Rate Estimation in HEVC.
IEEE Trans. Circuits Syst. Video Technol., 2022

A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO.
IEICE Electron. Express, 2022

2021
A Two-Step Phenotypic Parameter Measurement Strategy for Overlapped Grapes under Different Light Conditions.
Sensors, 2021

2020
A Highly Configurable 7.62GOP/s Hardware Implementation for LSTM.
IEICE Trans. Electron., 2020

Joint Network Function Deployment and Route Selection for Energy Consumption Optimization in SDN.
Proceedings of the 2020 International Conference on Wireless Communications and Signal Processing (WCSP), 2020

2019
A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation.
IEICE Trans. Electron., 2019

A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2018
A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation.
IEEE Trans. Circuits Syst. Video Technol., 2018

End-to-End Delay Minimization based Joint Route Selection and Network Function Placement in SDN.
Proceedings of the 10th International Conference on Wireless Communications and Signal Processing, 2018

A Compact and Configurable Long Short-Term Memory Neural Network Hardware Architecture.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

2017
A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding.
IEICE Trans. Electron., 2017

2016
A Combined Deblocking Filter and SAO Hardware Architecture for HEVC.
IEEE Trans. Multim., 2016

Quarter LCU based integer motion estimation algorithm for HEVC.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

68 Gbps quantum random number generation by measuring laser phase fluctuations.
CoRR, 2015

A flexible HEVC intra mode decision hardware for 8kx4k real time encoder.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A hardware-friendly method for rate-distortion optimization of HEVC intra coding.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2006
Quantum key distribution based on a Sagnac loop interferometer and polarization-insensitive phase modulators.
Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006


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