Lei Yang

Orcid: 0000-0002-0646-440X

Affiliations:
  • George Mason University, Department of Information Sciences and Technology, USA
  • University of Notre Dame, Department of Computer Science and Engineering, IN, USA
  • University of Pittsburgh, Department of Electrical and Computer Engineering, PA, USA
  • Chongqing University, College of Computer Science, China


According to our database1, Lei Yang authored at least 78 papers between 2014 and 2024.

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Timeline

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Bibliography

2024
Guest Editorial of the Special Section on Intelligent Computing for Big Data in Consumer Internet of Things.
IEEE Trans. Consumer Electron., May, 2024

A Physics-guided Generative AI Toolkit for Geophysical Monitoring.
CoRR, 2024

Self-guided Knowledge-Injected Graph Neural Network for Alzheimer's Diseases.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2024, 2024

Data-Algorithm-Architecture Co-Optimization for Fair Neural Networks on Skin Lesion Dataset.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2024, 2024

APS-USCT: Ultrasound Computed Tomography on Sparse Data via AI-Physic Synergy.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2024, 2024

TrojFair: Trojan Fairness Attacks.
Proceedings of the 1st ACM Workshop on Large AI Systems and Models with Privacy and Safety Analysis, 2024

Poster Abstract: Neural Architecture Sizing for Autonomous Systems.
Proceedings of the 15th ACM/IEEE International Conference on Cyber-Physical Systems, 2024

Enhanced AI for Science using Diffusion-based Generative AI - A Case Study on Ultrasound Computing Tomography.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Toward Fair Ultrasound Computing Tomography: Challenges, Solutions and Outlook.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

EdGeo: A Physics-guided Generative AI Toolkit for Geophysical Monitoring on Edge Devices.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Hardware-aware neural architecture search for stochastic computing-based neural networks on tiny devices.
J. Syst. Archit., February, 2023

Fast and Fair Medical AI on the Edge Through Neural Architecture Search for Hybrid Vision Models.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

On-Device Unsupervised Image Segmentation.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Toward Fair and Efficient Hyperdimensional Computing.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Seismic Waveform Inversion Capability on Resource-Constrained Edge Devices.
J. Imaging, December, 2022

Development of A Real-time POCUS Image Quality Assessment and Acquisition Guidance System.
CoRR, 2022

Federated Self-Supervised Contrastive Learning and Masked Autoencoder for Dermatological Disease Diagnosis.
CoRR, 2022

Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning.
CoRR, 2022

Automated Architecture Search for Brain-inspired Hyperdimensional Computing.
CoRR, 2022

RT-DNAS: Real-Time Constrained Differentiable Neural Architecture Search for 3D Cardiac Cine MRI Segmentation.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2022, 2022

Hardware-aware Automated Architecture Search for Brain-inspired Hyperdimensional Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

On the Design of Quantum Graph Convolutional Neural Network in the NISQ-Era and Beyond.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

The larger the fairer?: small neural networks can achieve fairness for edge devices.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

BSC: Block-based Stochastic Computing to Enable Accurate and Efficient TinyML.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
On the Design of Minimal-Cost Pipeline Systems Satisfying Hard/Soft Real-Time Constraints.
IEEE Trans. Emerg. Top. Comput., 2021

Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators.
IEEE Trans. Computers, 2021

Detecting Gender Bias in Transformer-based Models: A Case Study on BERT.
CoRR, 2021

Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow.
CoRR, 2021

HuGE: An Entropy-driven Approach to Efficient and Scalable Graph Embeddings.
Proceedings of the 37th IEEE International Conference on Data Engineering, 2021

Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning (Invited Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

FL-DISCO: Federated Generative Adversarial Network for Graph-based Molecule Drug Discovery: Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow (Invited Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Co-Exploration of Graph Neural Network and Network-on-Chip Design Using AutoML.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

HMC-TRAN: A Tensor-core Inspired Hierarchical Model Compression for Transformer-based DNNs on GPU.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Hardware/Software Co-Exploration of Neural Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CSMqGraph: Coarse-Grained and Multi-external-storage Multi-queue I/O Management for Graph Computing.
Int. J. Parallel Program., 2020

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Contention Minimized Bypassing in SMART NoC.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

MLND: A Weight-Adapting Method for Multi-label Classification Based on Neighbor Label Distribution.
Proceedings of the Web and Big Data - 4th International Joint Conference, 2020

2019
Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference.
ACM Trans. Embed. Comput. Syst., 2019

Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

On the Design of Time-Constrained and Buffer-Optimal Self-Timed Pipelines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router.
IEEE Trans. Computers, 2019

Hardware/Software Co-Exploration of Neural Architectures.
CoRR, 2019

XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Routing in optical network-on-chip: minimizing contention with guaranteed thermal reliability.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Chip Temperature Optimization for Dark Silicon Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained CNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.
IEEE Trans. Computers, 2018

Fine-Grained Task-Level Parallel and Low Power H.264 Decoding in Multi-Core Systems.
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018

User Experience-Enhanced and Energy-Efficient Task Scheduling on Heterogeneous Multi-Core Mobile Systems.
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018

On the Design of Reliable Heterogeneous Systems via Checkpoint Placement and Core Assignment.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Communication optimization for thermal reliable optical network-on-chip: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
Optimal Functional-Unit Assignment for Heterogeneous Systems Under Timing Constraint.
IEEE Trans. Parallel Distributed Syst., 2017

FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era.
IEEE Trans. Parallel Distributed Syst., 2017

Hardware-software collaboration for dark silicon heterogeneous many-core systems.
Future Gener. Comput. Syst., 2017

Fixed priority scheduling of real-time flows with arbitrary deadlines on smart NoCs: work-in-progress.
Proceedings of the Thirteenth ACM International Conference on Embedded Software 2017 Companion, 2017

Task Mapping on SMART NoC: Contention Matters, Not the Distance.
Proceedings of the 54th Annual Design Automation Conference, 2017

Communication optimization for thermal reliable many-core systems: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput.
J. Signal Process. Syst., 2016

Application Mapping and Scheduling for Network-on-Chip-Based Multiprocessor System-on-Chip With Fine-Grain Communication Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2016

FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systems.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
De-Frag: an efficient scheme to improve deduplication performance via reducing data placement de-linearization.
Clust. Comput., 2015

Prevent Deadlock and Remove Blocking for Self-Timed Systems.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014
Contention-aware task and communication co-scheduling for network-on-chip based Multiprocessor System-on-Chip.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

On self-timed ring for consistent mapping and maximum throughput.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014


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