Lei Wang

Orcid: 0000-0003-4689-791X

Affiliations:
  • University of Connecticut, Department of Electrical and Computer Engineering, Storrs, CT, USA


According to our database1, Lei Wang authored at least 82 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Boundary-Aware Deformable Spiking Neural Network for Hyperspectral Image Classification.
Remote. Sens., October, 2023

2021
Low-Power Non-Binary LDPC Decoder Design via Adaptive Message Length Control Exploiting Domain-Specific Information.
J. Signal Process. Syst., 2021

2020
A Memristor-Based Compressive Sampling Encoder with Dynamic Rate Control for Low-Power Video Streaming.
ACM J. Emerg. Technol. Comput. Syst., 2020

2019
Design for Test and Hardware Security Utilizing Retention Loss of Memristors.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Probabilistic Evaluation of Hardware Security Vulnerabilities.
ACM Trans. Design Autom. Electr. Syst., 2019

Design of Low-Power Non-Binary LDPC Decoder Exploiting DRAM Refresh Rate Over-Scaling.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Integrated power converter design for bioturbation resilience in multi-anode microbial fuel cells.
IET Circuits Devices Syst., 2019

2018
Design of GNSS Receivers Powered by Renewable Energy via Adaptive Tracking Channel Control.
J. Signal Process. Syst., 2018

Exploiting Memristors for Compressive Sampling of Sensory Signals.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Chip-Level Anti-Reverse Engineering Technique.
ACM J. Emerg. Technol. Comput. Syst., 2018

2017
Self-sustained UWB Sensing: A Link and Energy Adaptive Approach.
J. Signal Process. Syst., 2017

Improving DRAM Performance in 3-D ICs via Temperature Aware Refresh.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An FPGA-Based Architecture for High-Speed Compressed Signal Reconstruction.
ACM Trans. Embed. Comput. Syst., 2017

A memristor based image sensor exploiting compressive measurement for low-power video streaming.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A secure scan chain test scheme exploiting retention loss of memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An Energy Combiner Design for Multiple Microbial Energy Harvesting Sources.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Energy-Adaptive Signal Processing Under Renewable Energy.
J. Signal Process. Syst., 2016

A Survey on Chip to System Reverse Engineering.
ACM J. Emerg. Technol. Comput. Syst., 2016

A memristor-based compressive sensing architecture.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design of a shared-stage charge pump circuit for multi-anode microbial fuel cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Reverse engineering resistant ROM design using transformable via-programming structure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Tracking Data Flow at Gate-Level through Structural Checking.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
High-speed Signal Reconstruction for Compressive Sensing Applications.
J. Signal Process. Syst., 2015

Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement.
J. Signal Process. Syst., 2015

RF Power Management via Energy-Adaptive Modulation for Self-Powered Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Adaptive tracking channel control for GNSS receivers under renewable energy.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Temperature aware refresh for DRAM performance improvement in 3D ICs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Low-power LDPC decoder design exploiting memory error statistics.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Chip-level anti-reverse engineering using transformable interconnects.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Energy-adaptive Pulse Amplitude Modulation for IR-UWB Communications Under Renewable Energy.
J. Signal Process. Syst., 2014

Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Towards achieving long-lifespan and self-sustained monitoring of coastal environments.
Proceedings of the 2014 IEEE International Conference on Systems, Man, and Cybernetics, 2014

Energy-adaptive performance management for self-sustained signal processing systems.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

2013
An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory.
ACM J. Emerg. Technol. Comput. Syst., 2013

Digital health communities: The effect of their motivation mechanisms.
Decis. Support Syst., 2013

A biomass-based marine sediment energy harvesting system.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Link and energy adaptive UWB-based embedded sensing with renewable energy.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Soft-thresholding Orthogonal Matching Pursuit for efficient signal reconstruction.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
A Nonbinary LDPC Decoder Architecture With Adaptive Message Control.
IEEE Trans. Very Large Scale Integr. Syst., 2012

High-Speed Signal Reconstruction with Orthogonal Matching Pursuit via Matrix Inversion Bypass.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Energy-Adaptive Modulation for RF Power Management under Renewable Energy.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

2011
A framework for the impact of IT on organizational performance.
Bus. Process. Manag. J., 2011

Nonbinary LDPC decoding by min-sum with Adaptive Message Control.
Proceedings of the IEEE International Conference on Acoustics, 2011

2010
An information-theoretic analysis of quantum-dot cellular automata for defect tolerance.
ACM J. Emerg. Technol. Comput. Syst., 2010

Data rate maximization by adaptive thresholding RF power management under renewable energy.
Proceedings of the 28th International Conference on Computer Design, 2010

Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Analysis of Defect Tolerance in Molecular Crossbar Electronics.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Analysis of Deskew Signaling Via Adaptive Timing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation.
ACM J. Emerg. Technol. Comput. Syst., 2009

Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing.
ACM J. Emerg. Technol. Comput. Syst., 2009

A defect/error-tolerant nanosystem architecture for DSP.
ACM J. Emerg. Technol. Comput. Syst., 2009

A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

A Study of Side-Channel Effects in Reliability-Enhancing Techniques.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

IT's Impact on Organizational Performance: A Meta-Analysis.
Proceedings of the 15th Americas Conference on Information Systems, 2009

2008
Improving Error Tolerance for Multithreaded Register Files.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Defect-tolerant digital filtering with unreliable molecular electronics.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Cooperative OFDM for energy-efficient wireless sensor networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

A DSP nanosystem with defect tolerance.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Design of error-tolerant cache memory for multithreaded computing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Programmable threshold voltage using quantum dot transistors for low-power mobile computing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Making register file resistant to power analysis attacks.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Low-Complexity Analysis of Repetitive Regularities for Biometric Applications.
J. Comput., 2007

Dynamic redundancy allocation for reliable and high-performance nanocomputing.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Analysis of defect tolerance in molecular electronics using information-theoretic measures.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

2006
Thread-associative memory for multicore and multithreaded computing.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Adaptive timing for analysis of skew tolerance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reducing error accumulation effect in multithreaded memory systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Exploiting soft redundancy for error-resilient on-chip memory design.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Human IRIS Identification Via Low-Complexity Circular Periodicity Transform.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

2005
An energy-efficient skew compensation technique for high-speed skew-sensitive signaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Error-tolerance memory Microarchitecture via Dynamic Multithreading.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2003
Low-power MIMO signal processing.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Low-power filtering via adaptive error-cancellation.
IEEE Trans. Signal Process., 2003

2001
Designing Low-Power Communication Systems via Noise-Tolerance
PhD thesis, 2001

Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Energy-efficiency bounds for noise-tolerant dynamic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Noise-tolerant dynamic circuit design.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


  Loading...