Lei Liu
Orcid: 0000-0001-5063-2864Affiliations:
- Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Computer Architecture, Beijing, China
According to our database1,
Lei Liu
authored at least 38 papers
between 2008 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2022
ACM Trans. Archit. Code Optim., 2022
Optimizing deep neural networks on intelligent edge accelerators via flexible-rate filter pruning.
J. Syst. Archit., 2022
CCF Trans. High Perform. Comput., 2022
2021
Int. J. Parallel Program., 2021
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Int. J. Embed. Syst., 2020
Proceedings of the Network and Parallel Computing, 2020
Characterizing the I/O Pipeline in the Deployment of CNNs on Commercial Accelerators.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2020
Lance: efficient low-precision quantized winograd convolution for neural networks based on graphics processing units.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the Euro-Par 2020: Parallel Processing, 2020
2019
J. Comput. Sci. Technol., 2019
Int. J. Parallel Program., 2019
Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019
Proceedings of the Benchmarking, Measuring, and Optimizing, 2019
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018
Auto-tuning Neural Network Quantization Framework for Collaborative Inference Between the Cloud and Edge.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2018, 2018
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2018, 2018
2017
J. Exp. Theor. Artif. Intell., 2017
Int. J. Parallel Program., 2017
Proceedings of the Advanced Parallel Processing Technologies, 2017
2016
Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random?
IEEE Trans. Computers, 2016
J. Comput. Sci. Technol., 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
WiseThrottling: a new asynchronous task scheduler for mitigating I/O bottleneck in large-scale datacenter servers.
J. Supercomput., 2015
2014
BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems.
ACM Trans. Archit. Code Optim., 2014
Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms.
J. Comput. Sci. Technol., 2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
2013
Proceedings of the Network and Parallel Computing - 10th IFIP International Conference, 2013
2012
A software memory partition approach for eliminating bank-level interference in multicore systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Proceedings of the 26th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2011
2010
Unified Parallel C for GPU Clusters: Language Extensions and Compiler Implementation.
Proceedings of the Languages and Compilers for Parallel Computing, 2010
2008
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008
Global Tiling for Communication Minimal Parallelization on Distributed Memory Systems.
Proceedings of the Euro-Par 2008, 2008