Lei Jiang

Fan Chen

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2024

2023

Sky-Sorter: A Processing-in-Memory Architecture for Large-Scale Sorting.

[BibT_eX]

[DOI]

IEEE Trans. Computers, February, 2023

TrojFSP: Trojan Insertion in Few-shot Prompt Tuning.

[BibT_eX]

[DOI]

CoRR, 2023

LLMCarbon: Modeling the end-to-end Carbon Footprint of Large Language Models.

[BibT_eX]

[DOI]

CoRR, 2023

SSL-Cleanse: Trojan Detection and Mitigation in Self-Supervised Learning.

[BibT_eX]

[DOI]

CoRR, 2023

SePaint: Semantic Map Inpainting via Multinomial Diffusion.

[BibT_eX]

[DOI]

CoRR, 2023

CryptoQFL: Quantum Federated Learning on Encrypted Data.

[BibT_eX]

[DOI]

Cheng Chu

Fan Chen

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

QDoor: Exploiting Approximate Synthesis for Backdoor Attacks in Quantum Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

PriML: An Electro-Optical Accelerator for Private Machine Learning on Encrypted Data.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

QTROJAN: A Circuit Backdoor Against Quantum Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2023

Primer: Fast Private Transformer Inference on Encrypted Data.

[BibT_eX]

[DOI]

Mengxin Zheng

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

TrojViT: Trojan Insertion in Vision Transformers.

[BibT_eX]

[DOI]

Mengxin Zheng

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2022

Self-Supervised Pretraining for Differentially Private Learning.

[BibT_eX]

[DOI]

Arash Asadian

Evan Weidner

CoRR, 2022

FHEBench: Benchmarking Fully Homomorphic Encryption Schemes.

[BibT_eX]

[DOI]

Lei Ju

CoRR, 2022

CryptoLight: An Electro-Optical Accelerator for Fully Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

QMLP: An Error-Tolerant Nonlinear Quantum MLP Architecture using Parameterized Two-Qubit Gates.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

MATCHA: a fast and energy-efficient accelerator for fully homomorphic encryption over the torus.

[BibT_eX]

[DOI]

Nrushad Joshi

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

HEMET: A Homomorphic-Encryption-Friendly Privacy-Preserving Mobile Neural Network Architecture.

[BibT_eX]

[DOI]

Proceedings of the 38th International Conference on Machine Learning, 2021

SAFENet: A Secure, Accurate and Fast Neural Network Inference.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Learning Representations, 2021

EXMA: A Genomics Accelerator for Exact-Matching.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

CRYPTOGRU: Low Latency Privacy-Preserving Text Analysis With GRU.

[BibT_eX]

[DOI]

Proceedings of the 2021 Conference on Empirical Methods in Natural Language Processing, 2021

2020

AutoPrivacy: Automated Layer-wise Parameter Selection for Secure Neural Network Inference.

[BibT_eX]

[DOI]

Song Bian

Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

Falcon: Fast Spectral Inference on Encrypted Data.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

Glyph: Fast and Accurately Training Deep Neural Networks on Encrypted Data.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

AutoQ: Automated Kernel-Wise Neural Network Quantization.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Learning Representations, 2020

Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

LightBulb: A Photonic-Nonvolatile-Memory-based Accelerator for Binarized Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

MindReading: An Ultra-Low-Power Photonic Accelerator for EEG-based Human Intention Recognition.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Helix: Algorithm/Architecture Co-design for Accelerating Nanopore Genome Base-calling.

[BibT_eX]

[DOI]

Sarath Chandra Janga

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019

Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

SHE: A Fast and Accurate Privacy-Preserving Deep Neural Network Via Leveled TFHE and Logarithmic Data Representation.

[BibT_eX]

[DOI]

CoRR, 2019

A GraphBLAS Approach for Subgraph Counting.

[BibT_eX]

[DOI]

CoRR, 2019

AutoQB: AutoML for Network Quantization and Binarization on Mobile Devices.

[BibT_eX]

[DOI]

CoRR, 2019

SHE: A Fast and Accurate Deep Neural Network for Encrypted Data.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

HolyLight: A Nanophotonic Accelerator for Deep Learning in Data Centers.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Thermal Sensing Using Micro-ring Resonators in Optical Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory Architecture.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Fault-Tolerant Neural Network Architecture.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FindeR: Accelerating FM-Index-Based Exact Pattern Matching in Genomic Sequences through ReRAM Technology.

[BibT_eX]

[DOI]

Mingzhe Zhang

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs.

[BibT_eX]

[DOI]

Hamid R. Zarandi

IEEE Comput. Archit. Lett., 2018

BRAWL: A Spintronics-Based Portable Basecalling-in-Memory Architecture for Nanopore Genome Sequencing.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Performance Characterization of Multi-threaded Graph Processing Applications on Many-Integrated-Core Architecture.

[BibT_eX]

[DOI]

Langshi Chen

Judy Qiu

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

3DICT: a reliable and QoS capable mobile process-in-memory architecture for lookup-based CNNs in 3D XPoint ReRAMs.

[BibT_eX]

[DOI]

Wujie Wen

Proceedings of the International Conference on Computer-Aided Design, 2018

Repurposing SoC analog circuitry for additional COTS hardware security.

[BibT_eX]

[DOI]

Adam Duncan

Martin Swany

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

DeepN-JPEG: a deep neural network favorable JPEG-based image compression framework.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

DrAcc: a DRAM based accelerator for accurate CNN inference.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

PT-spike: A precise-time-dependent single spike neuromorphic architecture with efficient supervised learning.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture.

[BibT_eX]

[DOI]

Langshi Chen

Judy Qiu

CoRR, 2017

Addressing Read-Disturbance Issue in STT-RAM by Data Compression and Selective Duplication.

[BibT_eX]

[DOI]

Sparsh Mittal

Jeffrey S. Vetter

IEEE Comput. Archit. Lett., 2017

High-Performance Massive Subgraph Counting Using Pipelined Adaptive-Group Communication.

[BibT_eX]

[DOI]

Proceedings of the Big Data and HPC: Ecosystem and Convergence, TopHPC 2017, 2017

Constructing fast and energy efficient 1TnR based ReRAM crossbar memory.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short Writes.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Building a Fast and Power Efficient Inductive Charge Pump System for 3D Stacked Phase Change Memories.

[BibT_eX]

[DOI]

Sparsh Mittal

Wujie Wen

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A statistical STT-RAM retention model for fast memory subsystem designs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Benchmarking Harp-DAAL: High Performance Hadoop on KNL Clusters.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE 10th International Conference on Cloud Computing (CLOUD), 2017

2016

Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance.

[BibT_eX]

[DOI]

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

A low power and reliable charge pump design for Phase Change Memories.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Mitigating Write Disturbance in Super-Dense Phase Change Memories.

[BibT_eX]

[DOI]

Youtao Zhang

Jun Yang

Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

SLC-enabled Wear Leveling for MLC PCM Considering Process Variation.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

Compiler directed write-mode selection for high performance low power volatile PCM.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

2012

FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

ER: elastic RESET for low power and long endurance MLC based phase change memory.

[BibT_eX]

[DOI]

Youtao Zhang

Jun Yang

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Improving write operations in MLC phase change memory.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling.

[BibT_eX]

[DOI]

Youtao Zhang

Jun Yang

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

2010

Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

2008

Pre-synthesis resource generation and estimation for transport-triggered architecture (TTA)-like architecture.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

Software Pipelining with Minimal Loop Overhead on Transport Triggered Architecture.

[BibT_eX]

[DOI]