Lei Chen

Affiliations:
  • Beijing Microelectronics Technology Institute, China


According to our database1, Lei Chen authored at least 14 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Research on agile FPGA fault injection system.
Proceedings of the International Conference on Microelectronics, 2021

2017
Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA.
Proceedings of the 6th International Conference on Informatics, 2017

2016
A 3.75Gb/s CML output driver with configurable pre-emphasis in 65nm CMOS technology.
Proceedings of the 2nd International Conference on Communication and Information Processing, 2016

2015
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
Coordinating routing resources for hex pips test in island-style FPGAs (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
A configurable fault-tolerant glitch-free clock switching circuit.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Precision fault injection method based on correspondence between configuration bitstream and architecture (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
An accurate fault location method based on configuration bitstream analysis.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Study of an Automated Precise SEU Fault Injection Technique.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2009
A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

A novel BIST approach for testing input/output buffers in FPGAs.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
BIST approach for testing configurable logic and memory resources in FPGAs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A novel configurable no dead-zone digital phase detector design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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