Leendert M. Huisman

According to our database, Leendert M. Huisman authored at least 19 papers between 1983 and 2004.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2004

Diagnosing arbitrary defects in logic designs using single location at a time (SLAT).

Leendert M. Huisman

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Data Mining Integrated Circuit Fails with Fail Commonalities.

Leendert M. Huisman, Maroun Kassab, Leah Pastel

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Analysis and Design of Optimal Combinational Compactors.

Peter Wohl, Leendert M. Huisman

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2001

Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm.

Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1998

Diagnosis and characterization of timing-related defects by time-dependent light emission.

Daniel R. Knebel, Pia N. Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Correlations between path delays and the accuracy of performance prediction.

Leendert M. Huisman

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1995

Yield fluctuations and defect models.

Leendert M. Huisman

J. Electron. Test., 1995

1994

Highly Reliable Symmetric Networks.

Leendert M. Huisman, Sandip Kundu

IEEE Trans. Parallel Distributed Syst., 1994

The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability.

Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1992

A Small Test Generator for Large Designs.

Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Symbolic implication in test generation.

Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar

Proceedings of the conference on European design automation, 1991

1990

Fault simulation of logic designs on parallel processors with distributed memory.

Leendert M. Huisman, Raja Daoud

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988

TRIM: testability range by ignoring the memory.

Larry Carter, Leendert M. Huisman, Tom W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

SLS-a fast switch-level simulator [for MOS].

Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

The reliability of approximate testability measures.

Leendert M. Huisman

IEEE Des. Test, 1988

1986

SLS - a fast switch level simulator for verification and fault coverage analysis.

Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1984

Using a Hardware Simulation Engine for Custom MOS Structured Designs.

Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman

IBM J. Res. Dev., 1984

Fast Pass-Transistor Simulation for Custom MOS Circuits.

Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo

IEEE Des. Test, 1984

1983

Simulating pass transistor circuits using logic simulation machines.

Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo

Proceedings of the 20th Design Automation Conference, 1983