Lee D. Coraor

According to our database, Lee D. Coraor authored at least 25 papers between 1985 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Performance characterization of the dynamic programming obstacle detection algorithm.

Tarak Gandhi, Mau-Tsuen Yang, Rangachar Kasturi, Octavia I. Camps, Lee D. Coraor, Jeffrey McCandless

IEEE Trans. Image Process., 2006

2002

An architecture for a nondeterministic distributed simulator.

Marc Bumble, Lee D. Coraor

IEEE Trans. Veh. Technol., 2002

Real-Time Implementation of Obstacle Detection Algorithms on a Datacube MaxPCI Architecture.

Mau-Tsuen Yang, Tarak Gandhi, Rangachar Kasturi, Lee D. Coraor, Octavia I. Camps, Jeffrey McCandless

Real Time Imaging, 2002

2000

Detection of Obstacles in the Flight Path of an Aircraft.

Tarak Gandhi, Mau-Tsuen Yang, Rangachar Kasturi, Octavia I. Camps, Lee D. Coraor, Jeffrey McCandless

Proceedings of the 2000 Conference on Computer Vision and Pattern Recognition (CVPR 2000), 2000

Exploring CORSIM Runtime Characteristics: Profiling a Traffic Simulator.

Marc Bumble, Lee D. Coraor, Lily Elefteriadou

Proceedings of the Proceedings 33th Annual Simulation Symposium (SS 2000), 2000

1999

A global synchronization network for a non-deterministic simulation architecture.

Marc Bumble, Lee D. Coraor

Proceedings of the 31st conference on Winter simulation: Simulation, 1999

Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use.

David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor

Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Computing in Memory Architectures for Digital Image Processing.

Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno

Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Evaluation of Computing in Memory Architectures for Digital Image Processing Applications.

David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor

Proceedings of the IEEE International Conference On Computer Design, 1999

1998

Architecture for a Non-deterministic Simulation Machine.

Marc Bumble, Lee D. Coraor

Proceedings of the 30th conference on Winter simulation, 1998

Implementing Parallelism in Random Discrete Event-Driven Simulation.

Marc Bumble, Lee D. Coraor

Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

1995

Improving Cache Performance in a Multiprocessor Environment.

Jong S. Park, Lee D. Coraor

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1995

Program Balance and Its Impact on High Performance RISC Architectures.

Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

A comparative evaluation of software techniques to hide memory latency.

Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor

Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994

Memory Latency Effects in Decoupled Architectures.

Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor

IEEE Trans. Computers, 1994

Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories.

Lizyamma Kurian, Bermjae Choi, Paul T. Hulina, Lee D. Coraor

Proceedings of the 1994 International Conference on Parallel Processing, 1994

Structured Data Access Mechanisms for a Decoupled Computer Architecture.

Ali Berrached, Paul T. Hulina, Lee D. Coraor

Proceedings of the 1994 International Conference on Parallel Processing, 1994

1992

Design and VLSI implementation of an access processor for a decoupled architecture.

Paul T. Hulina, Lizyamma Kurian, Eugene B. John, Lee D. Coraor

Microprocess. Microsystems, 1992

Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module.

Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991

Classification and Performance Evaluation of Instruction Buffering Techniques.

Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

Performance Analysis of an Address Generation Coprocessor.

Paul T. Hulina, Lee D. Coraor, Shih-Wei Sun

Proceedings of the International Conference on Parallel Processing, 1991

1990

Coprocessor architectures for efficient address computation and memory accessing.

Paul T. Hulina, Lee D. Coraor

Comput. Syst. Sci. Eng., 1990

1987

A General Model for Memory-Based Finite-State Machines.

Lee D. Coraor, Paul T. Hulina, Orlando A. Morean

IEEE Trans. Computers, 1987

A Hardware Memory Mapping Unit for Efficient Address Computation.

Paul T. Hulina, Lee D. Coraor

Proceedings of the International Conference on Parallel Processing, 1987

1985

A Reconfigurable Multiprocessor.

Lee D. Coraor, Paul T. Hulina

Proceedings of the International Conference on Parallel Processing, 1985