Leandro Möller

According to our database1, Leandro Möller authored at least 23 papers between 2002 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2013
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.
ACM Trans. Embed. Comput. Syst., 2013

2012
Communication infrastructure modeling of many-core architectures.
PhD thesis, 2012

Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

2011
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

2010
Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms.
Int. J. Embed. Real Time Commun. Syst., 2010

Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

A case study of hierarchically heterogeneous application modelling using UML and Ptolemy II.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Characterising embedded applications using a UML profile.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Towards a unique FPGA-based identification circuit using process variations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Validation of executable application models mapped onto network-on-chip platforms.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

A simplified executable model to evaluate latency and throughput of networks-on-chip.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

2006
Infrastructure for dynamic reconfigurable systems: choices and trade-offs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Reconfigurable Systems Enabled by a Network-on-Chip.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2004
HERMES: an infrastructure for low area overhead packet-switching networks on chip.
Integr., 2004

FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.
Proceedings of the Field Programmable Logic and Application, 2004

MultiNoC: A Multiprocessing System Enabled by a Network on Chip.
Proceedings of the 2004 Design, 2004

2003
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Remote and Partial Reconfiguration of FPGAs: Tools and Trends.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs.
Proceedings of the 2003 Design, 2003

2002
Core Communication Interface for FPGAs.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002


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