Lawrence T. Clark

According to our database, Lawrence T. Clark authored at least 74 papers between 1989 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

ASAP5: A predictive PDK for the 5 nm node.

Vinay Vashishtha, Lawrence T. Clark

Microelectron. J., 2022

Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology.

Lawrence T. Clark, Alen Duvnjak, Clifford Young-Sciortino, Matthew Cannon, John S. Brunhaver, Sapan Agarwal, Jereme Neuendank, Donald Wilson, Hugh J. Barnaby, Matthew J. Marinella

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node.

Vinay Vashishtha, Lawrence T. Clark

Microelectron. J., 2021

2019

Physically Unclonable Functions Using Foundry SRAM Cells.

Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala, John S. Brunhaver

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells.

John S. Brunhaver, Richard Uhrie, Lawrence T. Clark

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory.

Lawrence T. Clark, James Adams, Keith E. Holbert

Integr., 2019

2018

SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability.

Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala

IEEE Trans. Very Large Scale Integr. Syst., 2018

2017

Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit.

Lawrence T. Clark, Vinay Vashishtha, David M. Harris, Samuel Dietrich, Zunyan Wang

Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit.

Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Integrated circuit identification and true random numbers using 1.5-transistor flash memory.

Lawrence T. Clark, James Adams, Keith E. Holbert

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Robust 7-nm SRAM design on a predictive PDK.

Vinay Vashishtha, Manoj Vangala, Parv Sharma, Lawrence T. Clark

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper.

Vinay Vashishtha, Manoj Vangala, Lawrence T. Clark

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Design with sub-10 nm FinFET technologies.

Lawrence T. Clark, Vinay Vashishtha

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

SRAM-Based Unique Chip Identifier Techniques.

Srivatsan Chellappa, Lawrence T. Clark

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits.

Lawrence T. Clark, Dan W. Patterson, Chandarasekaran Ramamurthy, Keith E. Holbert

IEEE Trans. Computers, 2016

ASAP7: A 7-nm finFET predictive process design kit.

Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric

Microelectron. J., 2016

2015

Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014).

José M. de la Rosa, Patrick Chiang, Lawrence T. Clark

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation.

Srivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Delay and power tradeoffs for static and dynamic register files.

Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Simple and accurate single event charge collection macro modeling for circuit simulation.

Aymeric Privat, Lawrence T. Clark

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU.

Sushil Kumar, Srivatsan Chellappa, Lawrence T. Clark

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A soft-error hardened process portable embedded microprocessor.

Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits.

Lawrence T. Clark, Sandeep Shambhulingaiah

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Methodology to optimize critical node separation in hardened flip-flops.

Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Transient response exploration of SRAM cell metastable states caused by ionizing radiation with 3D mixed mode simulation.

Aymeric Privat, Lawrence T. Clark, Hugh J. Barnaby

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Independent N and P process monitors for body bias based process corner correction.

Lawrence T. Clark, David Kidd, Vineet Agrawal, Samuel Leshner, Gokul Krishnan

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Low Complexity Out-of-Order Issue Logic Using Static Circuits.

Siddhesh S. Mhambrey, Satendra Kumar Maurya, Lawrence T. Clark

IEEE Trans. Very Large Scale Integr. Syst., 2013

Reducing Transistor Variability for High Performance Low Power Chips.

Robert Rogenmoser, Lawrence T. Clark

IEEE Micro, 2013

SRAM cell optimization for low AVT transistors.

Lawrence T. Clark, Samuel Leshner, George Tien

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias.

Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011

A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing.

Satendra Kumar Maurya, Lawrence T. Clark

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing.

Satendra Kumar Maurya, Lawrence T. Clark

J. Low Power Electron., 2011

Validation of and delay variation in total ionizing dose hardened standard cell libraries.

Lawrence T. Clark, David E. Pettit, Keith E. Holbert, Nathan D. Hindman

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Efficient voltage conversion for SRAM low standby power modes.

Lawrence T. Clark, Tai-Hua Chen, Vikas Chaudhary

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Improved circuits for microchip identification using SRAM mismatch.

Srivatsan Chellappa, Aritra Dey, Lawrence T. Clark

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Fast and scalable priority encoding using static CMOS.

Satendra Kumar Maurya, Lawrence T. Clark

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Fast low power translation lookaside buffers using hierarchical NAND match lines.

Lawrence T. Clark, Vikas Chaudhary

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Out-of-order issue logic using sorting networks.

Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

In-situ characterization and extraction of SRAM variability.

Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark

Proceedings of the 47th Design Automation Conference, 2010

Single event transient mitigation in cache memory using transient error checking circuits.

Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith E. Holbert

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Low-Power Race-Free Programmable Logic Arrays.

Giby Samson, Lawrence T. Clark

IEEE J. Solid State Circuits, 2009

Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference.

Lawrence T. Clark, Anthony Chan Carusone, Payam Heydari

IEEE J. Solid State Circuits, 2009

Reducing process variation impact on replica-timed static random access memory sense timing.

Nishith N. Desai, Jonathan R. Haigh, Lawrence T. Clark

Integr., 2009

Low power fast and dense longest prefix match content addressable memory for IP routers.

Satendra Kumar Maurya, Lawrence T. Clark

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008

Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories.

Giby Samson, Nagaraj Ananthapadmanabhan, Sayeed A. Badrudduza, Lawrence T. Clark

IEEE J. Solid State Circuits, 2008

Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference.

Lawrence T. Clark, Ranjit Gharpurey, Payam Heydari

IEEE J. Solid State Circuits, 2008

Leakage Controlled Read Stable Static Random Access Memories.

Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Lawrence T. Clark

J. Comput., 2008

High performance set associative translation lookaside buffers for low power microprocessors.

Jonathan R. Haigh, Lawrence T. Clark

Integr., 2008

Critical race-free low-power nand match line content addressable memory tagged cache memory.

Vikas Chaudhary, Tai-Hua Chen, F. Sheerin, Lawrence T. Clark

IET Comput. Digit. Tech., 2008

Amorphous silicon logic circuits on flexible substrates.

Rahul Shringarpure, Lawrence T. Clark, Sameer M. Venugopal, David R. Allee, Shrinivas G. Uppili

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach.

Yu Cao, Lawrence T. Clark

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability.

Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity.

Lawrence T. Clark, Mohammed Kabir, Jonathan E. Knudsen

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability.

Sayeed A. Badrudduza, Lawrence T. Clark

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Low-power high-performance nand match line content addressable memories.

Vikas Chaudhary, Lawrence T. Clark

IEEE Trans. Very Large Scale Integr. Syst., 2006

An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage.

Jinhui Chen, Lawrence T. Clark, Tai-Hua Chen

IEEE J. Solid State Circuits, 2006

Subthreshold to Above Threshold Level Shifter Design.

Tai-Hua Chen, Jinhui Chen, Lawrence T. Clark

J. Low Power Electron., 2006

Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power.

Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark

J. Low Power Electron., 2006

Circuit architecture for low-power race-free programmable logic arrays.

Giby Samson, Lawrence T. Clark

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A 0.13 μm Low-power Race-free Programmable Logic Array.

Giby Samson, Lawrence T. Clark

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A low-power 2.5-GHz 90-nm level 1 cache and memory management unit.

Jonathan R. Haigh, Michael W. Wilkerson, Jay B. Miller, Timothy S. Beatty, Stephen J. Strazdus, Lawrence T. Clark

IEEE J. Solid State Circuits, 2005

Low standby power state storage for sub-130-nm technologies.

Lawrence T. Clark, Franco Ricci, Manish Biyani

IEEE J. Solid State Circuits, 2005

Robust Design of High Fan-In/Out Subthreshold Circuits.

Jinhui Chen, Lawrence T. Clark, Yu Cao

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Reducing power in flexible a-Si digital circuits while preserving state.

Kyle R. Wissmiller, Jonathan E. Knudsen, Travis J. Alward, Zi P. Li, David R. Allee, Lawrence T. Clark

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Reverse-body bias and supply collapse for low effective standby power.

Lawrence T. Clark, M. Morrow, W. Brown

IEEE Trans. Very Large Scale Integr. Syst., 2004

Managing standby and active mode leakage power in deep sub-micron design.

Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003

Reducing translation lookaside buffer active power.

Lawrence T. Clark, Byungwoo Choi, Michael W. Wilkerson

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Trends and challenges for wireless embedded DSPs.

Lawrence T. Clark

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Standby power management for a 0.18µm microprocessor.

Lawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001

An embedded 32-b microprocessor core for low-power and high-performance applications.

Lawrence T. Clark, Eric J. Hoffman, Jay B. Miller, Manish Biyani, Yuyun Liao, Stephen J. Strazdus, Michael Morrow, Kimberley E. Velarde, Mark A. Yarch

IEEE J. Solid State Circuits, 2001

1996

High fan-in circuit design.

Lawrence T. Clark, Gregory F. Taylor

IEEE J. Solid State Circuits, 1996

1994

A 150 MHz 0.6 μm BiCMOS superscalar microprocessor.

Robert F. Krick, Lawrence T. Clark, Daniel J. Deleganes, Keng L. Wong, Roshan Fernando, Goutam Debnath, Jashojiban Banik

IEEE J. Solid State Circuits, December, 1994

1990

VLSI Implementation of Neural Classifiers.

Arun Rao, Mark R. Walker, Lawrence T. Clark, Lex A. Akers, Robert O. Grondin

Neural Comput., 1990

1989

A pipelined associated memory implemented in VLSI.

Lawrence T. Clark, Robert O. Grondin

IEEE J. Solid State Circuits, February, 1989