Lava Bhargava
Orcid: 0000-0002-6852-0227
According to our database1,
Lava Bhargava
authored at least 32 papers
between 2015 and 2024.
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Bibliography
2024
A Deep Learning Approach for the Detection of Intrusions with an Ensemble Feature Selection Method.
SN Comput. Sci., October, 2024
SN Comput. Sci., April, 2024
2023
Designing of Energy-Efficient Approximate Multiplier Circuit for Processing Unit of IoT Devices.
SN Comput. Sci., September, 2023
Enhanced Multicore Performance Using Novel Thread-Aware Cache Coherence and Prefetch-Control Mechanism.
IEEE Embed. Syst. Lett., March, 2023
LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Network Intrusion Classification on the UNSW-NB15 Dataset Using XGBoost Feature Selection Technique.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
Microprocess. Microsystems, June, 2022
Hybrid learning scenario path selection and abstraction framework for smart verification of complex SoCs.
J. Supercomput., 2022
Variability aware Golden Reference Free methodology for Hardware Trojan Detection Using Robust Delay Analysis.
CoRR, 2022
Deep neural network learning for power limited heterogeneous system with workload classification.
Computing, 2022
Comput. Ind. Eng., 2022
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
2021
J. Supercomput., 2021
Real-time automated register abstraction active power-aware electronic system level verification framework.
Integr., 2021
SRCP: sharing and reuse-aware replacement policy for the partitioned cache in multicore systems.
Des. Autom. Embed. Syst., 2021
Computing, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
2020
Automated Bug Resistant Test Intent with Register Header Database for Optimized Verification.
J. Electron. Test., 2020
2019
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019
Leakage Reduction and gm Enhancement in GaN HEMT for Enhanced Sensitivity in Fibrinogen Detection from Human Plasma.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019
2018
Novel Variability Aware Path Selection for Self-Referencing Based Hardware Trojan Detection.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Automated Coverage Register Access Technology on UVM Framework for Advanced Verification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
2016
Golden IC free methodology for hardware Trojan detection using symmetric path delays.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015