Lauri Koskinen
According to our database1,
Lauri Koskinen
authored at least 34 papers
between 2002 and 2024.
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Bibliography
2024
Shavette: Low Power Neural Network Acceleration via Algorithm-level Error Detection and Undervolting.
CoRR, 2024
2021
EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation.
IEEE Trans. Very Large Scale Integr. Syst., 2021
2020
A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020
Execution Frequency and Energy Optimization for DVFS-enabled, Near-threshold Processors.
Proceedings of the 10th International Conference on Advanced Computer Information Technologies, 2020
2018
Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
2017
Microelectron. J., 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Performance Case-Study on Memristive Computing-in-Memory Versus Von Neumann Architecture.
Proceedings of the 2016 Data Compression Conference, 2016
2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
SIGMOD Rec., 2014
Microelectron. J., 2014
A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Rethinking DC-DC converter design constraints for adaptable systems that target the minimum-energy point.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
2010
Proceedings of the IEEE International Conference on Acoustics, 2010
2009
IEEE J. Solid State Circuits, 2009
An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation.
EURASIP J. Adv. Signal Process., 2009
Proceedings of the Architecture of Computing Systems, 2009
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
A 1.5μW 1V 2<sup>nd</sup>-Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-Accelerometer.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Signal Process. Image Commun., 2007
Proceedings of the International Conference on Image Processing, 2007
2005
IEEE Trans. Circuits Syst. Video Technol., 2005
Parallel processor algorithm for variable block-size computation at low bitrates [video coding applications].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
3-neighborhood motion estimation in CNN silicon architectures.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002