Laurent Vachez
According to our database1,
Laurent Vachez
authored at least 4 papers
between 2010 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
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2020
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Bibliography
2020
High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technology.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2012
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC<sup>TM</sup> eFlash Memories.
J. Electron. Test., 2012
2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
A two-layer SPICE model of the ATMEL TSTAC<sup>TM</sup> eFlash memory technology for defect injection and faulty behavior prediction.
Proceedings of the 15th European Test Symposium, 2010