Laurent-Stéphane Didier

According to our database, Laurent-Stéphane Didier authored at least 21 papers between 1997 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Truncated multiplication and batch software SIMD AVX512 implementation for faster Montgomery multiplications and modular exponentiation.

Laurent-Stéphane Didier, Nadia El Mrabet, Léa Glandus, Jean-Marc Robert

IACR Commun. Cryptol., 2024

2022

A software comparison of RNS and PMNS.

Laurent-Stéphane Didier, Jean-Marc Robert, Fangan-Yssouf Dosso, Nadia El Mrabet

Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022

2021

Two hardware implementations for modular multiplication in the AMNS: Sequential and semi-parallel.

Asma Chaouch, Laurent-Stéphane Didier, Fangan-Yssouf Dosso, Nadia El Mrabet, Belgacem Bouallegue, Bouraoui Ouni

J. Inf. Secur. Appl., 2021

2020

Efficient modular operations using the adapted modular number system.

Laurent-Stéphane Didier, Fangan-Yssouf Dosso, Pascal Véron

J. Cryptogr. Eng., 2020

2019

Efficient and secure modular operations using the Adapted Modular Number System.

Laurent-Stéphane Didier, Fangan-Yssouf Dosso, Pascal Véron

CoRR, 2019

Hardware Optimization on FPGA for the Modular Multiplication in the AMNS Representation.

Asma Chaouch, Fangan-Yssouf Dosso, Laurent-Stéphane Didier, Nadia El Mrabet, Bouraoui Ouni, Belgacem Bouallegue

Proceedings of the Risks and Security of Internet and Systems, 2019

Randomization of Arithmetic Over Polynomial Modular Number System.

Laurent-Stéphane Didier, Fangan-Yssouf Dosso, Nadia El Mrabet, Jérémy Marrez, Pascal Véron

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2017

Hardware Division by Small Integer Constants.

H. Fatih Ugurdag, Florent de Dinechin, Y. Serhan Gener, Sezer Gören, Laurent-Stéphane Didier

IEEE Trans. Computers, 2017

2014

Formatting Bits to Better Implement Signal Processing Algorithms.

Benoit Lopez, Thibault Hilaire, Laurent-Stéphane Didier

Proceedings of the PECCS 2014, 2014

2013

Fast modulo 2ⁿ-1 and 2ⁿ;1 adder using carry-chain on FPGA.

Laurent-Stéphane Didier, Luc Jaulmes

Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012

Design of fixed-point embedded systems (DEFIS) French ANR project.

Daniel Ménard, Romuald Rocher, Olivier Sentieys, Nicolas Simon, Laurent-Stéphane Didier, Thibault Hilaire, Benoit Lopez, Eric Goubault, Sylvie Putot, Franck Védrine, Amine Najahi, Guillaume Revy, L. Fangain, Christian Samoyeau, Fabrice Lemonnier, Christophe Clienti

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Sum-of-products evaluation schemes with fixed-point arithmetic, and their application to IIR filter implementation.

Benoit Lopez, Thibault Hilaire, Laurent-Stéphane Didier

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Range estimation of floating-point variables in Simulink models.

Alexandre Chapoutot, Laurent-Stéphane Didier, Fanny Villers

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Table-Based Division by Small Integer Constants.

Florent de Dinechin, Laurent-Stéphane Didier

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2009

A Generalization of a Fast RNS Conversion for a New 4-Modulus Base.

Laurent-Stéphane Didier, Pierre-Yves Rivaille

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008

Une nouvelle base RNS à 4 moduli et son convertisseur vers le binaire.

Laurent-Stéphane Didier, Pierre-Yves Rivaille

Tech. Sci. Informatiques, 2008

2004

High Radix BKM Algorithm.

Laurent-Stéphane Didier, Fabien Rico

Numer. Algorithms, 2004

2001

Modular Multiplication and Base Extensions in Residue Number Systems.

Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup

Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

1998

A New Euclidean Division Algorithm for Residue Number Systems.

Jean-Claude Bajard, Laurent-Stéphane Didier, Jean-Michel Muller

J. VLSI Signal Process., 1998

An RNS Montgomery Modular Multiplication Algorithm.

Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup

IEEE Trans. Computers, 1998

1997

An IWS Montgomery Modular Multiplication Algorithm.

Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup

Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997