Laurent Souriau
Orcid: 0000-0002-5138-5938
According to our database1,
Laurent Souriau
authored at least 5 papers
between 2018 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
2018
2019
2020
2021
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On csauthors.net:
Bibliography
2021
Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.
Proceedings of the IEEE International Memory Workshop, 2021
2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018