Laurent Sauvage
Orcid: 0000-0002-6940-6856
According to our database1,
Laurent Sauvage
authored at least 39 papers
between 2008 and 2024.
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Bibliography
2024
EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
2023
IACR Cryptol. ePrint Arch., 2023
CoRR, 2023
High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSA.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2023
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2021
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
2020
Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020
2019
Proceedings of the Codes, Cryptology and Information Security, 2019
2018
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
2017
J. Cryptogr. Eng., 2017
How Far Can We Reach? Breaking RSM-Masked AES-128 Implementation Using Only One Trace.
IACR Cryptol. ePrint Arch., 2017
2016
Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016
Proceedings of the Information and Communications Security - 18th International Conference, 2016
2015
IACR Cryptol. ePrint Arch., 2015
2014
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.
J. Cryptogr. Eng., 2014
Proceedings of the Information Security Theory and Practice. Securing the Internet of Things, 2014
2012
Int. J. Reconfigurable Comput., 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Proceedings of the HOST 2011, 2011
2010
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics.
IEEE Trans. Computers, 2010
Int. J. Reconfigurable Comput., 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the Progress in Cryptology, 2010
Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks.
Proceedings of the Topics in Cryptology, 2010
2009
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.
ACM Trans. Reconfigurable Technol. Syst., 2009
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Computers, 2008
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.
Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.
Proceedings of the FPL 2008, 2008
Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008