Laurent Masse-Navette

According to our database, Laurent Masse-Navette authored at least 5 papers between 1991 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2019

Timing-Driven and Placement-Aware Multibit Register Composition.

Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2017

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation.

Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery

Proceedings of the 54th Annual Design Automation Conference, 2017

2015

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure.

Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization.

Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

1991

A Customizable Neural Processor for Distributed Neural Network.

J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, Laurent Masse-Navette

Proceedings of the VLSI 91, 1991