Laurent Fournier

According to our database1, Laurent Fournier authored at least 19 papers between 1999 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
RFC 7800 - Money Over IP.
CoRR, 2015

2014
Merchant Sharing Towards a Zero Marginal Cost Economy.
CoRR, 2014

2012
Économie des biens immatériels - Economics of Intangible Goods
CoRR, 2012

2011
A probabilistic analysis of coverage methods.
ACM Trans. Design Autom. Electr. Syst., 2011

Automatic boosting of cross-product coverage using Bayesian networks.
Int. J. Softw. Tools Technol. Transf., 2011

Reverse Coverage Analysis.
Proceedings of the Hardware and Software: Verification and Testing, 2011

2009
Using Bayesian networks and virtual coverage to hit hard-to-reach events.
Int. J. Softw. Tools Technol. Transf., 2009

2008
Automatic Boosting of Cross-Product Coverage Using Bayesian Networks.
Proceedings of the Hardware and Software: Verification and Testing, 2008

2007
Using Virtual Coverage to Hit Hard-To-Reach Events.
Proceedings of the Hardware and Software: Verification and Testing, 2007

A Framework for the Validation of Processor Architecture Compliance.
Proceedings of the 44th Design Automation Conference, 2007

2006
Advanced Analysis Techniques for Cross-Product Coverage.
IEEE Trans. Computers, 2006

DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005
Advanced analysis techniques for cross-product coverage.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2004
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.
IEEE Des. Test Comput., 2004

Micro-Architecture Verification for Microprocessors.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

2003
Solving the generalized mask constraint for test generation of binary floating point add operation.
Theor. Comput. Sci., 2003

FPgen - a test generation framework for datapath floating-point verification.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

1999
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family.
Proceedings of the 1999 Design, 1999

Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture.
Proceedings of the 36th Conference on Design Automation, 1999


  Loading...