Laurent Fournier
According to our database1,
Laurent Fournier
authored at least 19 papers
between 1999 and 2015.
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Bibliography
2015
2014
2012
2011
ACM Trans. Design Autom. Electr. Syst., 2011
Int. J. Softw. Tools Technol. Transf., 2011
Proceedings of the Hardware and Software: Verification and Testing, 2011
2009
Int. J. Softw. Tools Technol. Transf., 2009
2008
Proceedings of the Hardware and Software: Verification and Testing, 2008
2007
Proceedings of the Hardware and Software: Verification and Testing, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
2005
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
2004
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.
IEEE Des. Test Comput., 2004
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
2003
Solving the generalized mask constraint for test generation of binary floating point add operation.
Theor. Comput. Sci., 2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
1999
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family.
Proceedings of the 1999 Design, 1999
Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture.
Proceedings of the 36th Conference on Design Automation, 1999