Laurent Breuil

According to our database1, Laurent Breuil authored at least 8 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Gate Side Injection Operating Mode for 3D NAND Flash Memories.
Proceedings of the IEEE International Memory Workshop, 2024

2023
Enabling 3D NAND Trench Cells for Scaled Flash Memories.
Proceedings of the IEEE International Memory Workshop, 2023

Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND.
Proceedings of the IEEE International Memory Workshop, 2023

2022
High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction.
Proceedings of the IEEE International Memory Workshop, 2022

2021
Understanding the memory window in 1T-FeFET memories: a depolarization field perspective.
Proceedings of the IEEE International Memory Workshop, 2021

First demonstration of ferroelectric Si: HfO2 based 3D FE-FET with trench architecture for dense nonvolatile memory application.
Proceedings of the IEEE International Memory Workshop, 2021

2014
Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations.
Microelectron. Reliab., 2014


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