Laurence Pierre

According to our database, Laurence Pierre authored at least 44 papers between 1992 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions.

Laurence Pierre

Integr., 2021

2019

Assertion-Based Verification through Binary Instrumentation.

Enzo Brignon, Laurence Pierre

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Automated Testing for Cyber-physical Systems: From Scenarios to Executable Tests.

Martial Chabot, Laurence Pierre, Alexandre Nabais-Moreno

Proceedings of the 2018 Forum on Specification & Design Languages, 2018

2017

Assertion-Based Verification for SoC Models and Identification of Key Events.

Laurence Pierre, Martial Chabot

Proceedings of the Euromicro Conference on Digital System Design, 2017

2016

Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements.

Laurence Pierre

ACM Trans. Design Autom. Electr. Syst., 2016

A requirement driven testing method for multi-disciplinary system design.

Martial Chabot, Laurence Pierre, Alexandre Nabais-Moreno

Proceedings of the ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems, 2016

2015

Automatic and configurable instrumentation of C programs with temporal assertion checkers.

Martial Chabot, Kévin Mazet, Laurence Pierre

Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Towards a toolchain for assertion-driven test sequence generation.

Laurence Pierre

Proceedings of the 2015 Forum on Specification and Design Languages, 2015

2014

A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow.

Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems.

Martial Chabot, Laurence Pierre

Proceedings of the Testing Software and Systems, 2014

2013

On the Effectiveness of Assertion-Based Verification in an Industrial Context.

Laurence Pierre, Fabrice Pancher, Rodolphe Suescun, Jérôme Quévremont

Proceedings of the Formal Methods for Industrial Critical Systems, 2013

Automatic refinement of requirements for verification throughout the SoC design flow.

Laurence Pierre, Zeineb Bel Hadj Amor

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012

Integrating PSL properties into SystemC transactional modeling - Application to the verification of a modem SoC.

Laurence Pierre, Luca Ferro, Zeineb Bel Hadj Amor, Philippe Bourgon, Jérôme Quévremont

Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

A Mixed Verification Strategy Tailored for Networks on Chip.

Georgios Tsiligiannis, Laurence Pierre

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

A formal framework for testing with assertion checkers in mixed-signal simulation.

Laurence Pierre

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Towards Robustness Analysis Using PVS.

Renaud Clavel, Laurence Pierre, Régis Leveugle

Proceedings of the Interactive Theorem Proving - Second International Conference, 2011

Runtime Verification of Typical Requirements for a Space Critical SoC Platform.

Luca Ferro, Laurence Pierre, Zeineb Bel Hadj Amor, Jérôme Lachaize, Vincent Lefftz

Proceedings of the Formal Methods for Industrial Critical Systems, 2011

Improvement of Assertion-Based Verification through the generation of proper test sequences.

Laurence Pierre, Laila Damri

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Dynamic Verification of SystemC Transactional Models.

Laurence Pierre, Luca Ferro

Proceedings of the Model-Based Testing for Embedded Systems, 2011

2010

A Design Flow for Critical Embedded Systems.

Vincent Lefftz, Jean Bertrand, Hugues Cassé, Christophe Clienti, Philippe Coussy, Laurent Maillet-Contoz, Philippe Mercier, Pierre Moreau, Laurence Pierre, Emmanuel Vaumorin

Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

Enhancing the assertion-based verification of TLM designs with reentrancy.

Laurence Pierre, Luca Ferro

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing.

Amr Helmy, Laurence Pierre, Axel Jantsch

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Formal semantics for PSL modeling layer and application to the verification of transactional models.

Luca Ferro, Laurence Pierre

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A Formal Approach to the Verification of Networks on Chip.

Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz

EURASIP J. Embed. Syst., 2009

ISIS: Runtime verification of TLM platforms.

Luca Ferro, Laurence Pierre

Proceedings of the Forum on specification and Design Languages, 2009

Complementary Formal Approaches for Dependability Analysis.

Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

High-level symbolic simulation for automatic model extraction.

Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

A Tractable and Fast Method for Monitoring SystemC TLM Specifications.

Laurence Pierre, Luca Ferro

IEEE Trans. Computers, 2008

Executable formal specification and validation of NoC communication infrastructures.

Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

2007

A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study.

Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz

Proceedings of the First International Symposium on Networks-on-Chips, 2007

2004

Model-Checking Systems with Unbounded Variables without Abstraction.

Magali Contensin, Laurence Pierre

Proceedings of the Algebraic Methodology and Software Technology, 2004

2003

Formal Proof of Applications Distributed in Symmetric Interconnection Networks.

Eric Gascard, Laurence Pierre

Parallel Process. Lett., 2003

Combining ACL2 and a v-calculus Model-Checker to Verify System-Level Designs.

Magali Contensin, Laurence Pierre

Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

2002

Mechanical Verification of Hypercube Algorithms.

Eric Gascard, Laurence Pierre

Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001

Induction-Oriented Formal Verification in Symmetric Interconnection Networks.

Eric Gascard, Laurence Pierre

Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000

A compositional model for the functional verification of high-level synthesis results.

Dominique Borrione, Julia Dushina, Laurence V. Pierre

IEEE Trans. Very Large Scale Integr. Syst., 2000

1998

Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis.

Dominique Borrione, Julia Dushina, Laurence Pierre

Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

1996

Formal Specification of a Reactive System: An Exercise in VHDL, LOTOS and UNITY.

Laurence Pierre

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Describing and verifying synchronous circuits with the Boyer-Moore theorem prover.

Laurence Pierre

Proceedings of the Correct Hardware Design and Verification Methods, 1995

1994

An Automatic Generalization Method for the Inductive Proof of Replicated and Parallel Architectures.

Laurence Pierre

Proceedings of the Theorem Provers in Circuit Design, 1994

Formal verification of behavioral VHDL specifications: a case study.

Felix Nicoli, Laurence Pierre

Proceedings of the Proceedings EURO-DAC'94, 1994

Formal Verification of Hardware using LP and Comparison with Nqthm.

Michel Allemand, Felix Nicoli, Laurence Pierre

Proceedings of the 12st IASTED International Conference on Applied Informatics, 1994

1993

VHDL Description and Formal Verification of Systolic Multipliers.

Laurence Pierre

Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992

Formal Verification of VHDL Descriptions in the Prevail Environment.

Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem

IEEE Des. Test Comput., 1992