Laura Conde-Canencia
Orcid: 0000-0002-0057-5731
According to our database1,
Laura Conde-Canencia
authored at least 27 papers
between 2002 and 2022.
Collaborative distances:
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On csauthors.net:
Bibliography
2022
J. Signal Process. Syst., 2022
2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Proceedings of the 11th International Symposium on Topics in Coding, 2021
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the IEEE Global Communications Conference, 2018
2017
A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Extended-forward architecture for simplified check node processing in NB-LDPC decoders.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016
Proceedings of the 23rd International Conference on Telecommunications, 2016
Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
2015
Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories.
ACM J. Emerg. Technol. Comput. Syst., 2015
Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Non-binary coded CCSK and Frequency-Domain Equalization with simplified LLR generation.
Proceedings of the 24th IEEE Annual International Symposium on Personal, 2013
2012
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012
Modeling Adaptive Coded Modulation in real time partially reconfigurable mobile terminals.
Proceedings of the 20th European Signal Processing Conference, 2012
2011
J. Signal Process. Syst., 2011
2009
Non-Binary LDPC Codes Defined Over the General Linear Group: Finite Length Design and Practical Implementation Issues.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009
2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
2002
Application of the error impulse method in the design of high-order turbo coded modulation.
Proceedings of the 2002 IEEE Information Theory Workshop, 2002