Lars Wanhammar
Affiliations:- Linköping University, Sweden
According to our database1,
Lars Wanhammar
authored at least 60 papers
between 1987 and 2013.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
On csauthors.net:
Bibliography
2013
2011
Minimum adder depth multiple constant multiplication algorithm for low power FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
2008
IET Comput. Digit. Tech., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Implementation of Polyphase Decomposed FIR Filters for Interpolation and Decimation Using Multiple Constant Multiplication Techniques.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
Proceedings of the Integrated Circuit and System Design, 2004
A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Switching activity in bit-serial constant-coefficient multipliers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Multiplier blocks using carry-save adders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Two-channel digital and hybrid analog/digital multirate filter banks with very low-complexity analysis or synthesis filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Tree-structured IIR/FIR uniform-band and octave-band filter banks with very low-complexity analysis or synthesis filters.
Signal Process., 2003
J. Circuits Syst. Comput., 2003
Proceedings of the Integrated Circuit and System Design, 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Bit-level pipelinable general and fixed coefficient digit-serial/parallel multipliers based on shift-accumulation.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
Narrow-band and wide-band high-speed recursive digital filters using single filter frequency masking techniques.
Proceedings of the Sixth International Symposium on Signal Processing and its Applications, 2001
Arithmetic transformations for increased maximal sample rate of bit-parallel bireciprocal lattice wave digital filters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Tree-structured IIR/FIR octave-band filter banks with very low-complexity analysis filters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Implementation of bit-parallel lattice wave digital filters with increased maximal sample rate.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Decreasing the minimal sample period for recursive filters implemented using distributed arithmetic.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
A hardware efficient control of memory addressing for high-performance FFT processors.
IEEE Trans. Signal Process., 2000
High-speed, low-complexity fir filter using multiplier block reduction and polyphase decomposition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
A class of two-channel approximately perfect reconstruction hybrid analog/digital filter banks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Design and efficient implementation of high-speed narrow-band recursive digital filters using single filter frequency masking techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Design of m-channel tree-structured filter banks with very low-complexity analysis filters.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Proceedings of the 10th European Signal Processing Conference, 2000
Proceedings of the 10th European Signal Processing Conference, 2000
Design and efficient implementation of narrow-band single filter frequency masking FIR filters.
Proceedings of the 10th European Signal Processing Conference, 2000
1999
Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space representation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Implementation of a combined high-speed interpolation and decimation wave digital filter.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
A design procedure for 2-channel mixed analog and digital filter banks for A/D conversion using minimax optimization.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Maximally fast scheduling of bit-serial lattice wave digital filters using constrained third-order sections.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of the 8th European Signal Processing Conference, 1996
Two-stage polyphase interpolators and decimators for sample rate conversions with prime numbers.
Proceedings of the 8th European Signal Processing Conference, 1996
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the Mobile Communications: Advanced Systems and Components, 1994
1987