Lars Middendorf

According to our database1, Lars Middendorf authored at least 13 papers between 2007 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Statistical analysis and improvement of the repeatability and reproducibility of an evaluation method for IMUs on a smartphone.
Proceedings of the 8th ACM SIGCHI Symposium on Engineering Interactive Computing Systems, 2016

2015
A Mobile Camera-Based Evaluation Method of Inertial Measurement Units on Smartphones.
Proceedings of the Internet of Things. IoT Infrastructures, 2015

Dynamic task mapping of graphics processing applications on many-core architectures through stream rewriting.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

2014
Dynamic task scheduling and binding for many-core systems through stream rewriting.
PhD thesis, 2014

Scheduling of Recursive and Dynamic Data-Flow Graphs Using Stream Rewriting.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

2013
A Programmable Graphics Processor based on Partial Stream Rewriting.
Comput. Graph. Forum, 2013

Dynamic task mapping onto multi-core architectures through stream rewriting.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

A novel graphics processor architecture based on partial stream rewriting.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Using stream rewriting for mapping and scheduling data flow graphs onto many-core architectures.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Hardware synthesis of recursive functions through partial stream rewriting.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010
Declarative Programming with Handel-C.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2007
Embedded Vertex Shader in FPGA.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007


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