Lars Braun

According to our database, Lars Braun authored at least 24 papers between 2004 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Methoden zur Erstellung eines laufzeitadaptiven und zweidimensional rekonfigurierbaren Systems.

Lars Braun

PhD thesis, 2013

2012

Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices.

Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker

Int. J. Reconfigurable Comput., 2012

2011

Dynamic Processor Reconfiguration.

Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker.

Matthias Rümmele-Werner, Thomas Perschke, Lars Braun, Michael Hübner, Jürgen Becker

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.

Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker

Proceedings of the Design, Automation and Test in Europe, 2011

Development of a method for image-based motion estimation of a VTOL-MAV on FPGA.

Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker

Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Run-time resource instantiation for fault tolerance in FPGAs.

Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, Luigi Carro

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems.

Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker

ACM Trans. Reconfigurable Technol. Syst., 2010

Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space.

Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration.

Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration.

Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Two Dimensional Dynamic Multigrained Reconfigurable Hardware.

Lars Braun, Jürgen Becker

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies.

Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker

Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture.

Lars Braun, Diana Göhringer, Thomas Perschke, Volker Schatz, Michael Hübner, Jürgen Becker

J. Real Time Image Process., 2009

FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.

Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores.

Alexander Klimm, Lars Braun, Jürgen Becker

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.

Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.

Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker

Proceedings of the FPL 2008, 2008

Data path driven waveform-like reconfiguration.

Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker

Proceedings of the FPL 2008, 2008

Fine grain reconfigurable architectures.

Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker

Proceedings of the FPL 2008, 2008

Data reallocation by exploiting FPGA configuration mechanisms.

Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.

Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.

Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach

Proceedings of the FPL 2007, 2007

2004

Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.

Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker

Proceedings of the Field Programmable Logic and Application, 2004