Lars Bengtsson
Orcid: 0000-0001-6897-327X
According to our database1,
Lars Bengtsson
authored at least 34 papers
between 1993 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
1995
2000
2005
2010
2015
2020
0
1
2
3
4
1
1
2
1
3
2
1
3
1
1
1
1
1
1
2
3
2
1
3
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Inf. Manag., July, 2023
2021
Business Model Flexibility and Software-intensive Companies: Opportunities and Challenges.
e Informatica Softw. Eng. J., 2021
2020
Int. J. Manuf. Technol. Manag., 2020
2017
A High Throughput Anticollision Protocol to Decrease the Energy Consumption in a Passive RFID System.
Wirel. Commun. Mob. Comput., 2017
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2017
2016
An Energy and Identification Time Decreasing Procedure for Memoryless RFID Tag Anticollision Protocols.
IEEE Trans. Wirel. Commun., 2016
J. Comput. Inf. Syst., 2016
Int. J. Technol. Manag., 2016
2013
Int. J. Technol. Manag., 2013
2010
EURASIP J. Wirel. Commun. Netw., 2010
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010
2009
Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems.
J. Signal Process. Syst., 2009
Int. J. Manuf. Technol. Manag., 2009
Behav. Inf. Technol., 2009
2008
Int. J. Technol. Manag., 2008
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008
2007
Int. J. Technol. Manag., 2007
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
2006
Proceedings of the International Symposium on Industrial Embedded Systems, 2006
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
Proceedings of the Second Conference on Computing Frontiers, 2005
2004
Proceedings of the Integrated Circuit and System Design, 2004
2003
A VLSI Array Architecture for Artificial Neural Networks.
Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence, 2003
DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures.
Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003
Proceedings of the Advances in Computer Systems Architecture, 2003
2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
1999
Clock Speed Limitation and Timing in a Radar Signal Processing Architecture.
Proceedings of the Signal and Image Processing (SIP), 1999
1997
PhD thesis, 1997
1993
Microprocess. Microprogramming, 1993