Larry L. Biro

According to our database1, Larry L. Biro authored at least 8 papers between 1991 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

1995
2000
2005
2010
0
1
2
3
1
2
1
1
2
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012
A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers.
IEEE J. Solid State Circuits, 2012

2011
A 32nm 3.1 billion transistor 12-wide-issue Itanium<sup>®</sup> processor for mission-critical servers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

1998
Circuit implementation of a 600 MHz superscalar RISC microprocessor.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Power Considerations in the Design of the Alpha 21264 Microprocessor.
Proceedings of the 35th Conference on Design Automation, 1998

1992
A 100-MHz macropipelined VAX microprocessor.
IEEE J. Solid State Circuits, November, 1992

The NVAX and NVAX+ High-Performance VAX Microprocessor.
Digit. Tech. J., 1992

1991
Timing Verification on a 1.2M-Device Full-Custom CMOS Design.
Proceedings of the 28th Design Automation Conference, 1991


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