Lance Hammond

According to our database1, Lance Hammond authored at least 17 papers between 1996 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Author's retrospective for: improving the performance of speculatively parallel applications on the hydra CMP.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2007
iChip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01720-9, 2007

2006
Executing Java programs with transactional memory.
Sci. Comput. Program., 2006

"Software Performance Tuning with the Apple CHUD Tools".
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

2005
The future of microprocessors.
ACM Queue, 2005

TAPE: a transactional application profiling environment.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Characterization of TCC on Chip-Multiprocessors.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004
Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software.
IEEE Micro, 2004

Transactional Memory Coherence and Consistency.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Programming with transactional coherence and consistency (TCC).
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2000
The Stanford Hydra CMP.
IEEE Micro, 2000

1999
Improving the performance of speculatively parallel applications on the Hydra CMP.
Proceedings of the 13th international conference on Supercomputing, 1999

1998
Data Speculation Support for a Chip Multiprocessor.
Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997
A Single-Chip Multiprocessor.
Computer, 1997

The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
Evaluation of Design Alternatives for a Multiprocessor Microprocessor.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

The Case for a Single-Chip Multiprocessor.
Proceedings of the ASPLOS-VII Proceedings, 1996


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