Lana Josipovic

Orcid: 0000-0001-6659-8533

Affiliations:
  • ETH Zurich, Switzerland
  • EPFL, Lausanne, Switzerland (former)


According to our database1, Lana Josipovic authored at least 31 papers between 2016 and 2025.

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Bibliography

2025
CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024
Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

DynaRapid: Fast-Tracking from C to Routed Circuits.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

DynaRapid: From C to FPGA in a Few Seconds.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

FPGA EDA - Design Principles and Implementation
Springer, ISBN: 978-981-99-7754-3, 2024

2023
Resource Sharing in Dataflow Circuits.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

Parallelising Control Flow in Dynamic-scheduling High-level Synthesis.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Buffer Placement and Sizing for High-Performance Dataflow Circuits.
ACM Trans. Reconfigurable Technol. Syst., 2022

From C/C++ Code to High-Performance Dataflow Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

29th Reconfigurable Architectures Workshop (RAW 2022).
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Load-Store Queue Sizing for Efficient Dataflow Circuits.
Proceedings of the International Conference on Field-Programmable Technology, 2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Dynamic Inter-Block Scheduling for HLS.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
High-Level Synthesis of Dynamically Scheduled Circuits.
PhD thesis, 2021

2020
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Combining Dynamic & Static Scheduling in High-level Synthesis.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Speculative Dataflow Circuits.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
Dynamically Scheduled High-level Synthesis.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
An Out-of-Order Load-Store Queue for Spatial Computing.
ACM Trans. Embed. Comput. Syst., 2017

From C to elastic circuits.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Enriching C-based High-Level Synthesis with parallel pattern templates.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016


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