Lana Josipovic

According to our database, Lana Josipovic authored at least 31 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2025

CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS.

Jiahui Xu, Lana Josipovic

Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024

Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits.

Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, Lana Josipovic

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

DynaRapid: Fast-Tracking from C to Routed Circuits.

Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing.

Jiahui Xu, Lana Josipovic

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

DynaRapid: From C to FPGA in a Few Seconds.

Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits.

Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

FPGA EDA - Design Principles and Implementation

Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipovic, Zhufei Chu

Springer, ISBN: 978-981-99-7754-3, 2024

2023

Resource Sharing in Dataflow Circuits.

Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Parallelising Control Flow in Dynamic-scheduling High-level Synthesis.

Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification.

Jiahui Xu, Lana Josipovic

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization.

Hanyu Wang, Carmine Rizzi, Lana Josipovic

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking.

Jiahui Xu, Emmet Murphy, Jordi Cortadella, Lana Josipovic

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits.

Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits.

Carmine Rizzi, Andrea Guerrieri, Lana Josipovic

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Buffer Placement and Sizing for High-Performance Dataflow Circuits.

Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella

ACM Trans. Reconfigurable Technol. Syst., 2022

From C/C++ Code to High-Performance Dataflow Circuits.

Lana Josipovic, Andrea Guerrieri, Paolo Ienne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis.

Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

29th Reconfigurable Architectures Workshop (RAW 2022).

Jürgen Becker, Lana Josipovic, Viktor K. Prasanna, Marco D. Santambrogio, Ramachandran Vaidyanathan

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Load-Store Queue Sizing for Efficient Dataflow Circuits.

Jiantao Liu, Carmine Rizzi, Lana Josipovic

Proceedings of the International Conference on Field-Programmable Technology, 2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits.

Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery.

Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Dynamic Inter-Block Scheduling for HLS.

Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021

High-Level Synthesis of Dynamically Scheduled Circuits.

Lana Josipovic

PhD thesis, 2021

2020

Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits.

Lana Josipovic, Andrea Guerrieri, Paolo Ienne

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Combining Dynamic & Static Scheduling in High-level Synthesis.

Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs.

Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne

Proceedings of the International Conference on Field-Programmable Technology, 2019

Speculative Dataflow Circuits.

Lana Josipovic, Andrea Guerrieri, Paolo Ienne

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Dynamically Scheduled High-level Synthesis.

Lana Josipovic, Radhika Ghosal, Paolo Ienne

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

An Out-of-Order Load-Store Queue for Spatial Computing.

Lana Josipovic, Philip Brisk, Paolo Ienne

ACM Trans. Embed. Comput. Syst., 2017

From C to elastic circuits.

Lana Josipovic, Philip Brisk, Paolo Ienne

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016

Enriching C-based High-Level Synthesis with parallel pattern templates.

Lana Josipovic, Nithin George, Paolo Ienne

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016