Lalitha Mohana Kalyani-Garimella

According to our database, Lalitha Mohana Kalyani-Garimella authored at least 5 papers between 2006 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow.

Lalitha Mohana Kalyani-Garimella, Sri Raga Sudha Garimella

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2013

New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A.

Lalitha Mohana Kalyani-Garimella, Sri Raga Sudha Garimella, Kevin Duda, Eric S. Fetzer

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2008

An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators.

Jaime Ramírez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio J. López-Martín, Ramón González Carvajal

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Low voltage gain boosting schemes for one stage operational amplifiers.

Jaime Ramírez-Angulo, Annajirao Garimella, Lalitha Mohana Kalyani-Garimella, Milind S. Sawant, Antonio Lopez-Martin, Ramón González Carvajal

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs.

Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006