Laleh Behjat

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

2023

How ChatGPT can inspire and improve serious board game design.

[BibT_eX]

[DOI]

Int. J. Serious Games, November, 2023

Design of an Integrated Project-Based Learning Curriculum: Analysis Through Fink's Taxonomy of Significant Learning.

[BibT_eX]

[DOI]

IEEE Trans. Educ., October, 2023

CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes.

[BibT_eX]

[DOI]

Aysa Fakheri Tabrizi

ACM Trans. Design Autom. Electr. Syst., September, 2023

RL-Ripper: : A Framework for Global Routing Using Reinforcement Learning and Smart Net Ripping Techniques.

[BibT_eX]

[DOI]

Upma Gandhi

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning.

[BibT_eX]

[DOI]

Renan Netto

Sheiny Fabre

Vinicius S. Livramento

Laércio Lima Pilla

José Luís Güntzel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Routability-Driven Detailed Placement Using Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

EDAML 2022 Invited Speaker 5: Combining Optimization and Machine Learning in Physical Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

E-RVP: An Initial Design Rule Violation Predictor Using Placement Information.

[BibT_eX]

[DOI]

Sheiny Fabre Almeida

Aysa Fakheri Tabrizi

Renan Netto

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Design Decisions Matter: Conveying the Importance of Software Engineering Best Practices through Hybrid PBL.

[BibT_eX]

[DOI]

Proceedings of the IEEE Frontiers in Education Conference, 2022

Hidden curriculum: students' reflections and observations.

[BibT_eX]

[DOI]

Robyn Paul

Robert Brennan

Proceedings of the IEEE Frontiers in Education Conference, 2022

CR&P: An Efficient Co-operation between Routing and Placement.

[BibT_eX]

[DOI]

Aysa Fakheri Tabrizi

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

ILP-Based Global Routing Optimization with Cell Movements.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020

Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

An Optimized Cost Flow Algorithm to Spread Cells in Detailed Placement.

[BibT_eX]

[DOI]

Jucemar Monteiro

Marcelo O. Johann

ACM Trans. Design Autom. Electr. Syst., 2019

2018

Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

A machine learning framework to identify detailed routing short violations from a placed netlist.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Detailed routing violation prediction during placement using machine learning.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

DATC RDF: Robust design flow database: Invited paper.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

An efficient optimal clock network buffer sizing with slew consideration.

[BibT_eX]

[DOI]

Ali Farshidi

Logan Rakai

Abubakr Hassan Abdelhafiz

Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016

Eh?Placer: A High-Performance Modern Technology-Driven Placer.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

A High-Performance Complexity Reduced Behavioral Model and Digital Predistorter for MIMO Systems With Crosstalk.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2016

A fast force-directed simulated annealing for 3D IC partitioning.

[BibT_eX]

[DOI]

Integr., 2016

Routing-Aware Incremental Timing-Driven Placement.

[BibT_eX]

[DOI]

Ricardo Augusto da Luz Reis

Andrew A. Kennings

Marcelo O. Johann

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

OpenDesign flow database: the infrastructure for VLSI design and design automation research.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Exploring Electrical Engineering through movement: Going with the Flow and Programming Puzzles.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

Using gamification for engagement and learning in electrical and computer engineering classrooms.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

2015

Enhancing EDA education through gamification.

[BibT_eX]

[DOI]

Emily Marasco

William D. Rosehart

Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

The impact of industry-organized contests on EDA education.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

A Detailed Routing-Aware Detailed Placement Technique.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

High Performance Global Placement and Legalization Accounting for Fence Regions.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Optimal gate sizing using a self-tuning multi-objective framework.

[BibT_eX]

[DOI]

Integr., 2014

Detailed placement accounting for technology constraints.

[BibT_eX]

[DOI]

Andrew A. Kennings

Nima Karimpour Darav

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

2013

A new a priori net length estimation technique for integrated circuits using radial basis functions.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2013

An analog-design assistant tool and an example of its application.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Integrating creativity into elementary electrical engineering education using CDIO and project-based learning.

[BibT_eX]

[DOI]

Emily Marasco

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

ISPD 2013 expert designer/user session (eds).

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

A New Length-Based Algebraic Multigrid Clustering Algorithm.

[BibT_eX]

[DOI]

VLSI Design, 2012

An algebraic multigrid-based algorithm for circuit clustering.

[BibT_eX]

[DOI]

Appl. Math. Comput., 2012

Analysis of post-placement length estimation.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

Parallel clock tree synthesis.

[BibT_eX]

[DOI]

Logan M. Rakai

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011

A pre-placement individual net length estimation model and an application for modern circuits.

[BibT_eX]

[DOI]

Integr., 2011

Wirelength and congestion estimation for routability-driven placement.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2009

A Multilevel Congestion-Based Global Router.

[BibT_eX]

[DOI]

VLSI Design, 2009

A pre-placement net length estimation technique for mixed-size circuits.

[BibT_eX]

[DOI]

Bahareh Fathi

Logan M. Rakai

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

2007

Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement.

[BibT_eX]

[DOI]

Andrew A. Kennings

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An effective clustering algorithm for mixed-size placement.

[BibT_eX]

[DOI]

Jie Huang

Proceedings of the 2007 International Symposium on Physical Design, 2007

Two Clustering Preprocessing Techniques for Large-Scale Circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Floorplan repair using dynamic whitespace management.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Clustering algorithms for circuit partitioning and placement problems.

[BibT_eX]

[DOI]

Logan Rakai

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

A connectivity based clustering algorithm with application to VLSI circuit partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Integer Linear Programming Models for Global Routing.

[BibT_eX]

[DOI]

William D. Rosehart

INFORMS J. Comput., 2006

Interior point models for power system stability problems.

[BibT_eX]

[DOI]

William D. Rosehart

Codruta Roman

Eur. J. Oper. Res., 2006

A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Net cluster: a net-reduction based clustering preprocessing algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

2005

A Multivalue Eigenvalue Based Circuit Partitioning Technique.

[BibT_eX]

[DOI]

Blair Schiffner

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A Structure Based Clustering Algorithm with Applications to VLSI Physical Design.

[BibT_eX]

[DOI]

Blair Schiffner

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Coordinated static stability margin management of inter-regional electricity systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fast integer linear programming based models for VLSI global routing.

[BibT_eX]

[DOI]

Andy Chiang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003

Steiner Tree Construction Based on Congestion for the Global Routing Problem.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

2002

A Novel Eigenvector Technique for Large Scale Combinatorial Problems in VLSI Layout.

[BibT_eX]

[DOI]

Dorothy Kucar

J. Comb. Optim., 2002

1999

VLSI concentric partitioning using interior point quadratic programming.

[BibT_eX]

[DOI]