Lakshminarayanan Renganarayanan

According to our database1, Lakshminarayanan Renganarayanan authored at least 14 papers between 2003 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2012
Parameterized loop tiling.
ACM Trans. Program. Lang. Syst., 2012

2011
Automatic Loop Tiling for Direct Memory Access.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Automatic creation of tile size selection models.
Proceedings of the CGO 2010, 2010

DMATiler: revisiting loop tiling for direct memory access.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

A model for fusion and code motion in an automatic parallelizing compiler.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Compact multi-dimensional kernel extraction for register tiling.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

2008
Positivity, posynomials and tile size selection.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

A domain specific interconnect for reconfigurable computing.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

2007
Multi-level tiling: M for the price of one.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

Parameterized tiled loops for free.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

Towards Optimal Multi-level Tiling for Stencil Computations.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2005
Combined ILP and Register Tiling: Analytical Model and Optimization Framework.
Proceedings of the Languages and Compilers for Parallel Computing, 2005

2004
A Geometric Programming Framework for Optimal Multi-Level Tiling.
Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 2004

2003
Switched Memory Architectures-Moving Beyond Systolic Arrays.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003


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