Lake Bu

Orcid: 0000-0002-9450-6533

According to our database1, Lake Bu authored at least 28 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption.
CoRR, 2020

Quantum-Proof Lightweight McEliece Cryptosystem Co-processor Design.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

A Post-Quantum Secure Discrete Gaussian Noise Sampler.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

Towards Programmable All-Digital True Random Number Generator.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Design-flow Methodology for Secure Group Anonymous Authentication.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Design of secure and trustworthy system-on-chip architectures using hardware-based root-of-trust techniques
PhD thesis, 2019

SRASA: a Generalized Theoretical Framework for Security and Reliability Analysis in Computing Systems.
J. Hardw. Syst. Secur., 2019

Design of reliable storage and compute systems with lightweight group testing based non-binary error correction codes.
IET Comput. Digit. Tech., 2019

RASSS: a hijack-resistant confidential information management scheme for distributed systems.
IET Comput. Digit. Tech., 2019

Post-Quantum Cryptographic Hardware Primitives.
CoRR, 2019

A Lightweight McEliece Cryptosystem Co-processor Design.
CoRR, 2019

Bulwark: Securing implantable medical devices communication channels.
Comput. Secur., 2019

A secure and robust scheme for sharing confidential information in IoT systems.
Ad Hoc Networks, 2019

Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
Designing Secure Heterogeneous Multicore Systems from Untrusted Components.
Cryptogr., 2018

Adaptive and Dynamic Device Authentication Using Lorenz Chaotic Systems.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Hardening AES Hardware Implementations Against Fault and Error Inject Attacks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Preventing Neural Network Model Exfiltration in Machine Learning Hardware Accelerators.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
A Design of Secure and ReliableWireless Transmission Channel for Implantable Medical Devices.
Proceedings of the 3rd International Conference on Information Systems Security and Privacy, 2017

Crosstalk Free Coding Systems to Protect NoC Channels against Crosstalk Faults.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

RASSS: A perfidy-aware protocol for designing trustworthy distributed systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Design of Reliable and Secure Devices Realizing Shamir's Secret Sharing.
IEEE Trans. Computers, 2016

A hybrid self-diagnosis mechanism with defective nodes locating and attack detection for parallel computing systems.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
New byte error correcting codes with simple decoding for reliable cache design.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015


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