L. S. S. Pavan Kumar Chodisetti

According to our database, L. S. S. Pavan Kumar Chodisetti authored at least 5 papers in 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2024

A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Jhih-Ying Ke, Cheng-Yao Lo, Tzung-Je Lee, Lean Karlo Santos Tolentino

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

A 1-6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Bo-Hao Liao, Pradyumna Vellanki, Tzung-Je Lee

Microelectron. J., 2024

A single-chip PFM-controlled LED driver with 0.5% illuminance variation.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo

Microelectron. J., 2024

A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Pradyumna Vellanki

Integr., 2024

An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS Process.

Pradyumna Vellanki, Hung-Che Tseng, Ying-Xuan Chen, L. S. S. Pavan Kumar Chodisetti, Chua-Chin Wang

Proceedings of the 21st International SoC Design Conference, 2024