Kyuseung Han

Orcid: 0000-0002-9151-3447

According to our database¹, Kyuseung Han authored at least 27 papers between 2009 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

Day-Night architecture: Development of an ultra-low power RISC-V processor for wearable anomaly detection.

[BibT_eX]

[DOI]

J. Syst. Archit., 2024

STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs.

[BibT_eX]

[DOI]

Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

Optimizing Implementation of SNN for Embedded System.

[BibT_eX]

[DOI]

Hyeonguk Jang

Jae-Jin Lee

Kyuseung Han

Proceedings of the 26th International Conference on Advanced Communications Technology, 2024

2023

Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Developing an Ultra-low Power RISC-V Processor for Anomaly Detection.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Releasing the Memory Bottleneck to Display Video Correctly.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

2021

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2021

Developing a Multicore Platform Utilizing Open RISC-V Cores.

[BibT_eX]

[DOI]

IEEE Access, 2021

K-means Clustering-specific Lightweight RISC-V processor.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

2019

TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties.

[BibT_eX]

[DOI]

IEEE Des. Test, 2019

MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems.

[BibT_eX]

[DOI]

IEEE Access, 2019

Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

TEI-power: Temperature Effect Inversion-Aware Dynamic Thermal Management.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

2014

Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture.

[BibT_eX]

[DOI]

Kyuseung Han

Ganghee Lee

Kiyoung Choi

IEEE Trans. Dependable Secur. Comput., 2014

Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study.

[BibT_eX]

[DOI]

Integr., 2014

Leveraging parallelism in the presence of control flow on CGRAs.

[BibT_eX]

[DOI]

Jihyun Ryoo

Kyuseung Han

Kiyoung Choi

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA.

[BibT_eX]

[DOI]

Kyuseung Han

Junwhan Ahn

Kiyoung Choi

ACM Trans. Archit. Code Optim., 2013

Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture.

[BibT_eX]

[DOI]

Manhwee Jo

Kyuseung Han

Kiyoung Choi

Proceedings of the Multimedia and Ubiquitous Engineering, 2013

Compiling control-intensive loops for CGRAs with state-based full predication.

[BibT_eX]

[DOI]

Kyuseung Han

Kiyoung Choi

Jongeun Lee

Proceedings of the Design, Automation and Test in Europe, 2013

2012

State-based full predication for low power coarse-grained reconfigurable architecture.

[BibT_eX]

[DOI]

Kyuseung Han

Seongsik Park

Kiyoung Choi

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

A host-accelerator communication architecture design for efficient binary acceleration.

[BibT_eX]

[DOI]

Yangsu Kim

Kyuseung Han

Kiyoung Choi

Proceedings of the International SoC Design Conference, 2011

2010

Acceleration of control flow on CGRA using advanced predicated execution.

[BibT_eX]

[DOI]

Kyuseung Han

Jong Kyung Paek

Kiyoung Choi

Proceedings of the International Conference on Field-Programmable Technology, 2010

2009

Coarse-grained reconfigurable architecture for multiple application domains: a case study.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

Kyuseung Han

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