Kyunghwan Min
Orcid: 0000-0001-5488-1147
According to our database1,
Kyunghwan Min
authored at least 5 papers
between 2015 and 2024.
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Bibliography
2024
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.
IEEE J. Solid State Circuits, January, 2024
A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2015
Reliability of fine pitch COF: Influence of surface morphology and CuSn intermetallic compound formation.
Proceedings of the IEEE International Reliability Physics Symposium, 2015