We stand with Ukraine

We stand with Ukraine

Kyungho Ryu

Orcid: 0000-0002-0354-4797

According to our database¹, Kyungho Ryu authored at least 31 papers between 2010 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

Energy efficient deployment of aerial base stations for mobile users in multi-hop UAV networks.

[BibT_eX]

[DOI]

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Ad Hoc Networks, 2024

2023

A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond.

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Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

Multi-Objective Optimization of Energy Saving and Throughput in Heterogeneous Networks Using Deep Reinforcement Learning.

[BibT_eX]

[DOI]

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Sensors, 2021

2020

An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits.

[BibT_eX]

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IEEE Trans. Very Large Scale Integr. Syst., 2020

payGo: Incentive-Comparable Payment Routing Based on Contract Theory.

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IEEE Access, 2020

2018

All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate.

[BibT_eX]

[DOI]

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IEEE Trans. Very Large Scale Integr. Syst., 2018

2016

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator.

[BibT_eX]

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IEEE Trans. Very Large Scale Integr. Syst., 2016

All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme.

[BibT_eX]

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IEEE Trans. Very Large Scale Integr. Syst., 2016

All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator.

[BibT_eX]

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IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs.

[BibT_eX]

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IEEE Trans. Very Large Scale Integr. Syst., 2015

An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management.

[BibT_eX]

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IEEE Trans. Very Large Scale Integr. Syst., 2015

All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM.

[BibT_eX]

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IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies.

[BibT_eX]

[DOI]

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Seung-Hyuk Kang

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IEEE Trans. Very Large Scale Integr. Syst., 2014

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector.

[BibT_eX]

[DOI]

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IEEE Trans. Circuits Syst. II Express Briefs, 2014

An MTJ-based non-volatile flip-flop for high-performance SoC.

[BibT_eX]

[DOI]

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Seung-Hyuk Kang

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Int. J. Circuit Theory Appl., 2014

High-performance low-power magnetic tunnel junction based non-volatile flip-flop.

[BibT_eX]

[DOI]

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Seung-Hyuk Kang

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

ADDLL for Clock-Deskew Buffer in High-Performance SoCs.

[BibT_eX]

[DOI]

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IEEE Trans. Very Large Scale Integr. Syst., 2013

A comparative study of STT-MTJ based non-volatile flip-flops.

[BibT_eX]

[DOI]

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Seung-Hyuk Kang

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Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management.

[BibT_eX]

[DOI]

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Proceedings of the IEEE International Conference on Consumer Electronics, 2013

All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate.

[BibT_eX]

[DOI]

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Proceedings of the ESSCIRC 2013, 2013

All-digital 90° phase-shift DLL with a dithering jitter suppression scheme.

[BibT_eX]

[DOI]

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Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop.

[BibT_eX]

[DOI]

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Seung-Hyuk Kang

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IEEE Trans. Very Large Scale Integr. Syst., 2012

A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM).

[BibT_eX]

[DOI]

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Seung-Hyuk Kang

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IEEE Trans. Very Large Scale Integr. Syst., 2012

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator.

[BibT_eX]

[DOI]

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IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface.

[BibT_eX]

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IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Integration of dual channel timing formatter system for high speed memory test equipment.

[BibT_eX]

[DOI]

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Young-Seok Park

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Choong Keun Lee

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Proceedings of the International SoC Design Conference, 2012

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction.

[BibT_eX]

[DOI]

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Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

MTJ based non-volatile flip-flop in deep submicron technology.

[BibT_eX]

[DOI]

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Seung-Hyuk Kang

Proceedings of the International SoC Design Conference, 2011

2010

A DLL based clock generator for low-power mobile SoCs.

[BibT_eX]

[DOI]

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IEEE Trans. Consumer Electron., 2010

A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface.

[BibT_eX]

[DOI]

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IEEE Trans. Consumer Electron., 2010

Process variation tolerant all-digital multiphase DLL for DDR3 interface.

[BibT_eX]

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Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

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